MN8390-C PANASONIC [Panasonic Semiconductor], MN8390-C Datasheet - Page 3

• Manufacturer Part Number: MN8390-C
• Description: LCD Panel Source Driver
• Manufacturer: PANASONIC [Panasonic Semiconductor]

For Information Equipment
99 to 102
Pin No.
21 to 24
27 to 30
42 to 45
37 to 40
32 to 35
70 to 73
47 to 50
Pin Descriptions
CLK1 to 3
Symbol
STHR
STHL
OE
RL
D1
Output enable
Analog signal
Shift data I/O
Shift direction
Clock input
Pin Name
swiching
control
I/O
I/O
I
I
I
I
These are I/O pins for the bidirectional shift register.
The RL pin controls their I/O directions.
(1) Input
The pins provide input data to the shift register's first
stage. The shift register reads in this data at the rising
edge of the CLK1 signal.
(2) Output
In a cascade connection, the pins provide the data for
the synchronizing output stage synchronized with the
rising edge of the CLK1 signal.
This pin controls the shift direction for the
bidirectional shift register.
RL="H" : QA1
RL="L" : QC80
These pins provide the shift clock signals that the
sample-and-hold circuits use to generate the data for
the LCD drive output pins (QA1-QC80).
The following lists the relationships between these
clock signals and the output pins.
At each rising edge of this signal, the MN8390-C
switches between its two sample-and-hold circuits
and initiates output of new data. When the outputs
reach the drive potential, the MN8390-C
automatically reduces the drive power, but maintains
the outputs at the drive potential.
This pin controls the mapping between the three
analog inputs (VA, VB, and VC) and the drive
outputs (QA, QB, and QC).
RL
D1
H
H
L
CLK1 RL="H": QA1 to QA80
CLK2:
CLK3 RL="H": QC1 to QC80
L
Function Description
RL="L":
RL="L":
Output
STHR
Input
Input
VA
VA
VB
VC
VB
VC
QB1
QB80
QC1 to QC80
QB1 to QB80
QA1 to QA80
Output
QA1 to QA80
QA1 to QA80
QB1 to QB80
QC1 to QC80
QB1 to QB80
QC1 to QC80
STHL
Input
QC1
Output
QA80
QC80
MN8390-C
QA1