DM9161BIEP DAVICOM [Davicom Semiconductor, Inc.], DM9161BIEP Datasheet - Page 22

• Manufacturer Part Number: DM9161BIEP
• Description: Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

AD
00 CONTROL
01
02
03
04 Auto-Neg.
05
06 Auto-Neg.
16 Specified
17 Specified
18
19
20
21
22
23 DIS_connec
24
29
D
Expansion
STATUS
Advertise
Link Part.
Conf/Stat
Conf/Stat
8. MII Register Description
PWDOR
Specified
MDINTR
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where：
<Reset Value>:
Preliminary
Version: DM9161BI-12-DS-P01
July 16, 2008
PHYID1
PHYID2
RCVER
RSTLH
Config.
Name
PSCR
config
Ability
10T
t
(PIN#)
X
1
0
TSTSE1 TSTSE2 FORCE_
Reserve
Reset
4B5B
Lh_led_
Page
Page
Rsvd
Cap.
Next
Next
FDX
Int_sts
100
mode
BP
15
T4
LP
0
0
0
1
d
FLP Rcv
TX FDX
Enable
Lh_mdint
Bit set to logic one
Bit set to logic zero
No default value
Value latched in from pin # at reset
Loop
SCR
HDX
Reserve
Reserve
back
Cap.
Ack
Ack
100
BP
LP
14
LP
0
1
0
0
d
d
r
TX HDX
Remote
Lh_cabst
Speed
ALIGN
Enable
Reserve
Reserve
select
Fault
Cap.
FDX
HBE
TXSD
LP
RF
BP
13
10
1
1
0
1
d
s
d
BP_ADP
10 FDX
10 HDX Reserve
Reserved
FORCE_
Auto-N
Enable
Enable
Lh_isolat
SQUE
Reverse
Reserve
Cap.
OK
12
FEF
1
1
0
1
Reserved
Reserved
d
e
d
Reversed
10 HDX
Repeater
Power
Down
Fdx_msk Spd_msk Lnk_msk Int_msk Reserve
preamble
Enable
Cap.
Lh_rmii Lh_seril1
11
JAB
0
1
0
1
d
x
Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Reserved
Reverse
Isolate
amplitud
Adv
Serial
FC
FC
LP
10
10T
TX
0
0
0
d
0
e
Reserved
Restart
FEF_EN RMII_E
Auto-N
Reverse
Lh_repea
TX_PW
Adv
LP
9
0
0
T4
T4
d
Reserved
ter
R
0000
Duplex
TX FDX
TX FDX
Receiver Error Counter
PD10DR
Lh_testm
Full
Reserve
Adv
LP
8
1
1
N
ode
V
d
TX HDX
TX HDX
100LNK
Force
Coll.
Test
<Access Type>:
<Attribute (s)>:
Adv
MDIX_C
Reserve
Lh_op2
LP
PD100l
7
0
1
NTL
Model No.
d
d
001011
PHY ADDR [4:0]
RO = Read only
RW = Read/Write
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
TST_SE
10 FDX
10 FDX
Pream.
Supr.
Adv
AutoNeg
Reserve
Reserve
LP
L0
PDchip
Lh_op1
_dlpbk
6
1
0
d
d
10 HDX
10 HDX
LEDCO
Auto-N
Compl.
L_SEL
Reserved
Adv
LP
Reverse
Reserve
Mdix_fix
Lh_op0 Lh_phya
PDcrm
5
0
0
Value
d
d
RPDCTR
Remote
Pardet
Fault
Fault
-EN
Disconnect_counter
Mdix_do
Fdx_chg Spd_chg Lnk_chg Reserve
Reserve
PDaeq
4
0
0
wn
d4
d
Link Partner Protocol Selector Field
Advertised Protocol Selector Field
000_0000
LP Next
Pg Able
St. Mch
Reserved
Auto-N
Reset
Cap.
MonSel1 MonSel0 Rmii_acc
Lh_phya
Reserve
PDdrv
3
1
0
d3
d
Auto-N. Monitor Bit [3:0]
Next Pg
Pream.
Status
Supr.
Lh_phya
DM9161BI
Able
Reserve
Link
PDecli
2
0
0
Version No.
d2
d
0000
New Pg
Jabber
Detect
Sleep
mode
Lh_phya
Reserve
Rcv
PDeclo
1
0
0
d1
u
d
d
LP AutoN
LoopOut
Reverse
Remote
Polarity
PD_valu
Lh_phya
Reserve
Int_sts
Extd
Cap.
Cap.
PD10
0
1
1
d0
e
d
22