PE3238EK PEREGRINE [Peregrine Semiconductor Corp.], PE3238EK Datasheet - Page 9

• Manufacturer Part Number: PE3238EK
• Manufacturer: PEREGRINE [Peregrine Semiconductor Corp.]

Interface
Interface
PE3238
Product Specification
to B
register on the rising edge of Sclk, MSB (B
The enhancement register is double buffered to
prevent inadvertent control changes during serial
loading, with buffer capture of the serially entered
data performed on the falling edge of E_WR
according to the timing diagram shown in Figure
5. After the falling edge of E_WR, the data provide
control bits as shown in Table 8 with bit
functionality enabled by asserting the Enh input
“low”.
Table 7. Primary Register Programming
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
Table 8. Enhancement Register Programming
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
Document No. 70-0031-03 │ www.psemi.com
Parallel
Parallel
Serial*
Serial*
Mode
Direct
Mode
7
, are clocked serially into the enhancement
Enh
Enh
1
1
1
0
0
Bmode
Bmode
0
0
1
X
X
Smode
Smode
X
0
1
0
1
M2_WR rising edge load
R
D
B
0
MSB (first in)
5
3
0
Reserved
D
B
R
D
B
7
0
0
MSB (first in)
4
2
1
M
D
B
0
1
2
8
Reserved
M
D
B
0
0
3
7
D
B
1
6
Pre_en
0
Pre_en
) first.
D
B
7
4
M
M
D
B
Reserved
5
6
6
6
D
B
M1_WR rising edge load
5
2
M
M
D
B
5
6
5
5
M
M
D
B
4
4
7
4
Direct Interface Mode
Direct Interface Mode is selected by setting the
Bmode input “high”.
Counter control bits are set directly at the pins as
shown in Table 7. In Direct Interface Mode, main
counter inputs M
R
Power
E_WR rising edge load
down
4
M
M
D
B
D
B
and R
3
8
3
3
4
3
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
M
M
D
B
9
2
2
2
5
are internally forced low (“0”).
B
M
M
D
Counter
10
1
1
1
load
D
B
4
3
B
M
D
M
11
0
0
0
7
and M
B
R
D
R
12
3
7
3
output
MSEL
B
R
D
R
D
B
8
13
2
2
5
6
2
, and R Counter inputs
A_WR rising edge load
B
R
D
R
14
1
5
1
B
R
D
R
Prescaler
15
0
4
0
output
(last in) LSB
D
B
1
6
B
A
D
A
16
3
3
3
(last in) LSB
B
A
D
A
Page 9 of 15
17
2
2
2
f
c
B
, f
A
D
A
18
D
B
1
1
1
p
0
7
OE
B
A
D
A
19
0
0
0