IC41SV4105-100J ICSI [Integrated Circuit Solution Inc], IC41SV4105-100J Datasheet - Page 6

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IC41SV4105-100J

Manufacturer Part Number
IC41SV4105-100J
Description
1Mx4 bit Dynamic RAM with Fast Page Mode
Manufacturer
ICSI [Integrated Circuit Solution Inc]
Datasheet
IC41SV4105
ELECTRICAL CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted.)
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast page cycle.
5. Enables on-chip refresh and address counters.
6
Symbol Parameter
I
I
V
V
I
I
I
I
I
I
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
CC
CC
CC
CC
CC
CC
IL
IO
OH
OL
1
2
3
4
5
6
Input Leakage Current
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Standby Current: CMOS
Operating Current:
Random Read/Write
Average Power Supply Current
Operating Current:
Fast Page Mode
Average Power Supply Current
Refresh Current:
RAS-Only
Average Power Supply Current
Refresh Current:
CBR
Average Power Supply Current
(2,3,5)
(2,3)
(2,3,4)
(2,3,4)
(1)
Test Condition
Any input 0V ≤ V
Other inputs not under test = 0V
0V ≤ V
I
I
RAS, CAS ≥ V
RAS, CAS ≥ V
RAS, CAS,
Address Cycling, t
RAS = V
t
RAS Cycling, CAS ≥ V
t
RAS, CAS Cycling
t
Output is disabled (Hi-Z)
OH
OL
RC
RC
RC
= 2 mA
= t
= t
= t
= −2.0 mA
RC
RC
RC
OUT
(min.)
(min.)
(min.)
IL
, CAS ≥ V
≤ Vcc
CC
IH
IN
− 0.2V
RC
≤ Vcc
IH
= t
IH
RC
(min.)
REF
refresh requirement is exceeded.
Integrated Circuit Solution Inc.
Speed Min.
-100
-100
-100
-100
-50
-70
-50
-70
-50
-70
-50
-70
1.6
−5
−5
DR032-0A 10/29/2001
Max.
0.8
0.5
70
60
50
55
45
35
70
60
50
70
60
50
5
5
1
Unit
mA
mA
mA
mA
mA
mA
µA
µA
V
V

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