ICS91305YGILF-T ICSI [Integrated Circuit Solution Inc], ICS91305YGILF-T Datasheet
ICS91305YGILF-T
Related parts for ICS91305YGILF-T
ICS91305YGILF-T Summary of contents
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Integrated Circuit Systems, Inc. High Performance Communication Buffer General Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input ...
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ICS91305I Pin Descriptions ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs (Except REF ...
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ICS91305I Switching Characteristics PARAMETER SYMBOL Output period t1 Input period t1 Duty Cycle 1 Dt1 Duty Cycle 1 Dt2 1 Rise Time tr1 Fall Time 1 tf1 Delay, REF Rising Edge to CLKOUT Dr1 1, 2 Rising Edge Output to ...
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Output to Output Skew The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all ...
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ICS91305I N INDE X ARE 150 mil (Narrow Body) SOIC Ordering Information ICS91305yMILF-T Example: ICS XXXX y M LF- T Designation for tape and reel packaging RoHS Compliant (Optional) Package Type Revision ...
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... INDEX AREA Ordering Information ICS91305yGILF-T Example: ICS XXXX y G LF- T 0691F—06/03/05 c SYMBOL α α aaa VARIATIONS Reference Doc.: JEDEC Publication 95, MO-153 SEATING PLANE 10-0035 aaa C Designation for tape and reel packaging ...
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ICS91305I Revision History Rev. Issue Date Description 1. Resized Electrical Characteristics Table. F 6/3/2005 2. Updated LF Ordering Information from "Lead Free" to "RoHS Compliant". 0691F—06/03/05 8 Page # 3,6,7 ...