DM9000_09 DAVICOM [Davicom Semiconductor, Inc.], DM9000_09 Datasheet - Page 29

• Manufacturer Part Number: DM9000_09
• Description: ISA to Ethernet MAC Controller with Integrated 10/100 PHY
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Final
Version: DM9000-DS-F03
April 23, 2009
17.8-17.4
17.3-17.0
17.11-17.
17.15
17.14
17.13
17.12
16.1
16.0
Bit
9
PHYADR[4:0]
RESERVED
ANMB[3:0]
Bit Name
100HDX
100FDX
RLOUT
SLEEP
10HDX
10FDX
(PHYADR),
Default
0, RW
0, RW
1, RO
1, RO
1, RO
1, RO
0, RO
0, RO
RW
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M full duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M half duplex
mode. The software can read bit [15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 10M Full Duplex
mode. The software can read bit [15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 10M half duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
Reserved
Write as 0, ignore on read
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple
PHY entities must know the appropriate address of each PHY
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be
written to these bits
0 = MF preamble suppression bit off
Sleep Mode
Writing a 1 to this bit will cause PHY to enter the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
Remote Loopout Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
B3 b2 b1 b0
0
0
0
0
0
0
0
1
In IDLE State
Ability Match
Description
DM9000
29