DM9000_09 DAVICOM [Davicom Semiconductor, Inc.], DM9000_09 Datasheet - Page 19

• Manufacturer Part Number: DM9000_09
• Description: ISA to Ethernet MAC Controller with Integrated 10/100 PHY
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

6.22 Vendor ID Register (28H~29H)
6.23 Product ID Register (2AH~2BH)
6.24 Chip Revision Register (2CH)
6.25 Special Mode Control Register ( 2FH )
6.26 Memory Data Read Command without Address Increment Register (F0H)
6.27 Memory Data Read Command with Address Increment Register (F2H)
6.28 Memory Data Read_address Register (F4H~F5H)
6.29 Memory Data Write Command without Address Increment Register (F6H)
Final
Version: DM9000-DS-F03
April 23, 2009
6~3
7:0
7:0
7:0
7:0
7:0
Bit
Bit
Bit
Bit
7:0
7:0
7:0
7:0
7:0
Bit
Bit
Bit
Bit
7
2
1
0
RESERVED
MWCMDX
MRCMDX
CHIPR
MRCMD
Name
Name
Name
MDRAH
MDRAL
SM_EN
VIDH
PIDH
VIDL
PIDL
Name
Name
Name
Name
Name
FLC
FB1
FB0
0AH,RO
46H.RO
90H,RO
00H.RO
00H,RO
00H,R/W
00H,R/W
Default
Default
Default
Default
Default
Default
Default
Default
X,WO
X,RO
X,RO
0,RW
0,RW
0,RW
0,RW
0,RO
Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged
Read data from RX SRAM. After the read of this command, the read pointer is
increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit
respectively)
Memory Data Read_ address High Byte. It will be set to 0Ch, when IMR bit7 =1
Memory Data Read_ address Low Byte
Write data to TX SRAM. After the write of this command, the write pointer is
unchanged
Vendor ID High Byte (29H)
Vendor ID Low Byte (28H)
Product ID High Byte (2BH)
Product ID Low Byte (2AH)
CHIP Revision
Special Mode Enable
Reserved
Force Late Collision
Force Longest Back-off time
Force Shortest Back-off time
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Description
Description
Description
Description
Description
Description
Description
Description
DM9000
19