DM9000A_06 DAVICOM [Davicom Semiconductor, Inc.], DM9000A_06 Datasheet - Page 20

• Manufacturer Part Number: DM9000A_06
• Description: Ethernet Controller with General Processor Interface
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

6.15 Wake Up Control Register ( 0FH ) (in 8-bit mode)
6.16 Physical Address Register ( 10H~15H )
6.17 Multicast Address Register ( 16H~1DH )
6.18 General purpose control Register ( 1EH ) ( For 8 Bit mode only, For 16 bit mode, see reg . 34H)
Final
Version: DM9000A-17-DS-F01
May 10, 2006
6:4
Bit
7:6
Bit
7
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Bit
Bit
5
4
3
2
1
0
RESERVED
RESERVED
SAMPLEEN
SAMPLEST
MAGICEN
MAGICST
GPC64
LINKEN
LINKST
Name
Name
Name
Name
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
PAB5
PAB4
PAB3
PAB2
PAB1
PAB0
PH0,RO
Default
Default
Default
111,RO
E,RW
E,RW
E,RW
E,RW
E,RW
E,RW
X,RW
X,RW
X,RW
X,RW
X,RW
X,RW
X,RW
X,RW
P0,RW
P0,RW
P0,RW
P0,RO
P0,RO
P0,RO
Type
0,RO
P,
Physical Address Byte 5 (15H)
Physical Address Byte 4 (14H)
Physical Address Byte 3 (13H)
Physical Address Byte 2 (12H)
Physical Address Byte 1 (11H)
Physical Address Byte 0 (10H)
Multicast Address Byte 7 (1DH)
Multicast Address Byte 6 (1CH)
Multicast Address Byte 5 (1BH)
Multicast Address Byte 4 (1AH)
Multicast Address Byte 3 (19H)
Multicast Address Byte 2 (18H)
Multicast Address Byte 1 (17H)
Multicast Address Byte 0 (16H)
Reserved
General Purpose Control 6~4
Define the input/output direction of pins GP6~4 respectively.
These bits are all forced to “1”s, so pins GP6~4 are output only.
Reserved
When set, it enables Link Status Change Wake up Event
This bit will not be affected after software reset
When set, it enables Sample Frame Wake up Event
This bit will not be affected after software reset
When set, it enables Magic Packet Wake up Event
This bit will not be affected after software reset
When set, it indicates that Link Change and Link Status Change Event occurred
This bit will not be affected after software reset
When set, it indicates that the sample frame is received and Sample Frame Event
occurred. This bit will not be affected after software reset
When set, indicates the Magic Packet is received and Magic packet Event
occurred. This bit will not be affected after a software reset
Ethernet Controller with General Processor Interface
Description
Description
Description
Description
DM9000A
20