HY5PS1G421LM HYNIX [Hynix Semiconductor], HY5PS1G421LM Datasheet - Page 54

• Manufacturer Part Number: HY5PS1G421LM
• Description: 1Gb DDR2 SDRAM(DDP)
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 0.2 / Oct. 2005
Input Clock Frequency Change during Precharge Power Down
DDR2 SDRAM input clock frequency can be changed under following condition:
DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level.
A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input
clock frequency is allowed to change only within minimum and maximum operating frequency specified for the
particular speed grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels.
Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power
down may be exited and DLL must be RESET via EMRS after precharge power down exit. Depending on new
clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL etc.. During
DLL re-lock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock
frequency.
Clock Frequency Change in Precharge Power Down Mode
CMD
CKE
ODT
CK
CK
T0
tAOFD
tRP
NOP
T1
NOP
Minmum 2 clocks
required before
changing frequency
T2
T4
Frequency Change
Occurs here
Tx
Tx+1
Ty
Stable new clock
before power down exit
Ty+1
Ty+2
NOP
tXP
Ty+3
NOP
1HY5PS12421(L)M
HY5PS12821(L)M
Ty+4
DLL
RESET
200 Clocks
ODT is off during
DLL RESET
NOP
Tz
Valid
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