CMX625P4 CMLMICRO [CML Microcircuits], CMX625P4 Datasheet - Page 9

• Manufacturer Part Number: CMX625P4
• Description: ISDN TA POTS Interface
• Manufacturer: CMLMICRO [CML Microcircuits]

ISDN TA POTS Interface
(iii) The ‘D’ channel consists of two bits providing 16kbps for carrying D channel user data. This channel
(iv) The ‘Command/Indicate’ channels, labelled C/I0 and C/I1, provide real time status information
2001 Consumer Microcircuits Limited
The CMX625 cannot initiate MON communication directly in a multi-slave application. Each slave
must monitor the MON channel for its unique address in the first byte before processing the following
command. Each slave can therefore only drive the DU MON channel when specifically requested to
by the master.
is not used by the CMX625.
between devices connected via the IOM-2 bus. The C/I0 in channel 0 consists of 4 bits and the C/I1
in channel 1 is 6 bits wide. The C/I0 in channel 0 is not used.
The C/I1 channel is shared by all devices on the IOM-2 bus with no mechanism for determining and
resolving contention. If multiple slave devices are expected to drive the C/I1 channel then care must
be taken to allocate different bits to each device. An example of C/I1 channel usage would be 6 slave
devices each allocated one of the 6 C/I1 bits. When a slave requires attention it asserts its own bit,
which is detected by the master as a C/I1 value change (generating a processor interrupt). The
processor would then initiate MON1 communications with the appropriate slave and service its
request.
command/indicate purpose dependent on system design and number of slaves on the IOM-2 bus.
The C/I1 Channel Output Control Code is encoded as follows (bits 0, 1 and 2 of the IOM CONTROL
Register):
Code ‘000’ is provided to disable drive of the C/I1 channel for use when multiple slaves have
completely utilised the C/I1 channel resource. The Interrupt Mask Register settings are ignored and
the C/I1 bits are set to logic ‘1’.
For codes ‘001’ to ‘110’ a logic ‘0’ (Interrupt Request) is driven onto the appropriate C/I1 bit when the
Status Register bits contain an unmasked logic ‘1’ (set by the Interrupt Mask Register). This allows
other devices to use the remaining C/I bits for their own purposes. The master device would use the
change of the appropriate C/I bit to initiate a Status Register read from the CMX625.
Code ‘111’ and an unmasked Status Register (INTERRUPT MASK bits 2 to 7 are set to ‘1’) allows the
most significant 6 bits of the Status Register to be driven onto the C/I1 channel directly for use when
the CMX625 is the only slave utilising the C/I channel. If any of the Status bits are masked, by setting
the equivalent bit in the mask register to ‘0’, then a logic ’0’ will be routed to the appropriate C/I1 bit
and will not change.
Code (IOM Control Register,
C/I1 Channel Output Control
Bits 2, 1 and 0)
This is an example of one usage, but the C/I1 bits may be used for any real time
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
C/I1 bits 5-0 = all logic ‘1’, i.e. C/I1 output disabled
Interrupt Request (logic ‘0’) on C/I1 bit 0 )
Interrupt Request (logic ‘0’) on C/I1 bit 1 )
Interrupt Request (logic ‘0’) on C/I1 bit 2 ) all other bits logic ‘1’
Interrupt Request (logic ‘0’) on C/I1 bit 3 )
Interrupt Request (logic ‘0’) on C/I1 bit 4 )
Interrupt Request (logic ‘0’) on C/I1 bit 5 )
Status Register bits 7-2 on C/I1 bits 5-0
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C/I1 Channel Output Bit Content
CMX625
D/625/2