CMX625P4 CMLMICRO [CML Microcircuits], CMX625P4 Datasheet - Page 32

no-image

CMX625P4

Manufacturer Part Number
CMX625P4
Description
ISDN TA POTS Interface
Manufacturer
CMLMICRO [CML Microcircuits]
Datasheet
ISDN TA POTS Interface
Notes:
t
t
t
FSC
t
t
t
t
2001 Consumer Microcircuits Limited
DCL
DCL
R
FSCS
FSCH
DUDC
DUDF
T
Typical UART Timings (See Figures 9a and 9b)
T
T
T
/ t
FSK
DLY
DRDY
UFL
F
IOM-2 Bus Timing (See Figure 13)
1. These signals are requirements and are not under control of CMX625.
2. Condition C
DCL clock period in TE Mode
DCL clock period in non-TE Mode
DCL clock rise time / fall time
FSC period
FSC set-up time
FSC hold time
DU delay clock (data out)
DU delay frame (data out)
(delay through the modulator)
(1 bit period)
(¼ bit-period)
(¾ bit-period)
L
= 150pF.
Figure 13 IOM-2 Bus Timing Diagram
32
Notes
Notes
1
1
1
1
1
1
2
2
Min.
Min.
70
40
-
-
-
-
-
-
-
-
-
-
Typ.
Typ.
106
833
208
625
651
244
125
-
-
-
-
-
Max.
100
150
Max.
60
-
-
-
-
-
-
-
-
-
CMX625
D/625/2
Unit
Unit
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
ns
ns

Related parts for CMX625P4