ELANSC310 AMD [Advanced Micro Devices], ELANSC310 Datasheet - Page 41

• Manufacturer Part Number: ELANSC310
• Description: Single-Chip, 32-Bit, PC/AT Microcontroller
• Manufacturer: AMD [Advanced Micro Devices]

SRAM
When using SRAM instead of DRAM for main memory,
up to 16 Mbyte can be accessed, the SRAM being or-
ganized as one or two banks. Each bank is 16 bits wide
and is provided with a low and high byte select.
An SRAM memory interface is selected by setting bit 0
of the Miscellaneous 6 Register, Index 70h. If this is
done, CAS1H, CAS1L, CAS0H, and CAS0L will have
their alternate function as SRAM chip select pins 3–0
(SRCS3–SRCS0). Table 17 shows the key SRAM ac-
cess pins.
See Table 14 on page 39 for bank size settings.
The PMU Modes and Clock Generators
The Power Management Unit (PMU) monitors all sys-
tem activities (e.g., keyboard, screen, and disk events),
and, based on the state of the system, determines in
which operating mode the system should be running.
The PMU supports six operating modes, each defined
by a different combination of CPU and peripheral oper-
ation, as shown in the list that follows.
1. High-Speed PLL. All clocks are at their fastest
2. Low-Speed PLL. The internal CPU clock is re-
3. Doze. The second level of power conservation. The
Notes:
Refer to Index 70h, bit 0, in the Élan
on how to select SRAM versus DRAM.
speed and all peripherals are powered up. This is
the mode the system enters when activity is de-
tected by the PMU.
duced to a maximum of 4.608 MHz. All other clocks
and peripherals operate at full speed. This is the
first level of power conservation; it is entered after a
specified elapsed time with no activity.
CPU, system, and DMA clocks are stopped. The
high-speed PLL is turned off. This mode is entered
after a specified elapsed time with no activity.
Index 63h
Bit 4
x
0
1
Configuration
Bits 1 and 0
Index 66h
0 0
0 1
0 1
TM
Table 18. SRAM Wait State Select Logic
Élan™SC310 Microcontroller Data Sheet
SC310 Microcontroller Programmer’s Reference Manual , order #20665 for information
P R E L I M I N A R Y
Read
Number of Wait States
0
1
2
The MS2–MS0 bits in the Memory Configuration Reg-
ister, Index 66h, are also used to program the total
SRAM size. Bit 7 of Index Register B4h must be
cleared for SRAM configurations. Table contains infor-
mation about SRAM wait state logic, and Table 28 on
page 61 contains SRAM interface alternate pin infor-
mation.
4. Sleep. Additional clocks and peripherals are
5. Suspend. Virtually all of the system is shut down,
6. Off. This level is virtually the same as Suspend
In addition, the ÉlanSC310 microcontroller can man-
age the power consumption of peripheral devices. This
control can be forced upon entering a specific operat-
ing mode or it can be handled directly by firmware. The
ÉlanSC310 microcontroller PMU controls five power
SRCS0
SRCS1
SRCS2
SRCS3
SA23–SA1
MWE
Write
Pin Name
stopped after additional inactivity has been de-
tected. The exact parameters can be programmed.
The Low-Speed PLL can be left on, so a quick star-
tup is possible.
including all clocks, the 8254 timer, and the Phase
Locked Loops (a programmable recovery time is
associated with this mode). The 32.768 kHz clock
input is still running.
mode. Two outputs can be programmed to change
state when the transition from Suspend mode to Off
mode occurs. DRAM refresh can be disabled in
OFF mode.
1
1
2
Table 17. SRAM Access Pins
20 MHz
I/O
O
O
O
O
O
0
120 ns
45 ns
80 ns
SRAM Bank 0 Low Byte Select
SRAM Bank 0 High Byte Select
SRAM Bank 1 Low Byte Select
SRAM Bank 1 High Byte Select
Address (16-Mbyte maximum)
Write enable
SRAM Speed
25 MHz
100 ns
Function
35 ns
55 ns
33 MHz
25 ns
35 ns
70 ns
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