ELANSC310 AMD [Advanced Micro Devices], ELANSC310 Datasheet - Page 104

• Manufacturer Part Number: ELANSC310
• Description: Single-Chip, 32-Bit, PC/AT Microcontroller
• Manufacturer: AMD [Advanced Micro Devices]

Notes:
1. This is the timing when DOSCS is qualified with MEMR or MEMW, (Bit 4 of ROM Configuration 3 Register, Index B8h, = 0).
2. This is the timing when DOSCS is configured as an address decode, (Bit 4 of ROM Configuration 3 Register, Index B8h, = 1).
These timings are based on Index 51h, bit 1 set for 16-bit DOSCS cycles and required initial programming. The standard DOS
ROM timings are based on the default wait state setting in bits 2 and 3 of the MMM Memory Wait States Register, Index 62h, for
4 wait states.
The Fast DOS ROM timings are based on Index B8h, bit 7 set for DOSCS to run at high speed with the default settings in bits 5
and 6 for 4 wait states. These timings may be modified via the Command Delay Register, Index 60h. (See the Élan
Microcontroller Programmer’s Reference Manual , order #20665.)
For more information about fast DOS ROM cycles, see the Élan
cation Note , order #20747.
104
Symbol
t11a
t11b
t16a
t16b
t1a
t1b
t2a
t2b
t3a
t3b
t4a
t4b
t5a
t5b
t10
t12
t13
t14
t15
t6
t7
t8
t9
SA stable to DOSCS active
SA stable to DOSCS active
SA hold from DOSCS inactive (write)
SA hold from DOSCS inactive (read)
DOSCS pulse width (read)
DOSCS pulse width (write)
MEMW active to DOSCS active
MEMR active to DOSCS active
DOSCS hold from MEMW inactive
DOSCS hold from MEMR inactive
RDDATA setup to command inactive
RDDATA hold from command inactive
WRDATA setup to command inactive
WRDATA hold from command inactive
DBUFOE active from command
DBUFOE hold from MEMW
DBUFOE hold from MEMR
ENDIRH, ENDIRL setup to MEMR
ENDIRH, ENDIRL hold from MEMR
DOSCS active to command active
DOSCS hold from SA
MEMR pulse width
MEMW pulse width
Table 54. DOS ROM and Fast DOS ROM Read/Write 16-Bit Cycles (See Figure 43)
Parameter Description
Élan™SC310 Microcontroller Data Sheet
P R E L I M I N A R Y
Notes
1
1
2
1
2
1
1
1
1
1
1
2
TM
SC300 and Élan
Preliminary
Min
550
500
400
550
500
65
50
25
45
50
–2
50
–4
65
Standard
0
0
0
0
5
DOS
Max
5
3
4
5
TM
SC310 Devices’ ISA Bus Anomalies Appli-
Preliminary
Min
130
100
120
130
100
25
15
25
15
15
–2
15
–4
15
Fast DOS
0
0
0
0
5
33 MHz
Max
5
3
4
5
Preliminary
Min
250
175
160
250
175
25
20
33
20
20
20
–4
20
Fast DOS
0
0
0
0
0
5
25 MHz
Max
8
3
4
0
TM
Units
SC310
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns