8S89834AKILF IDT [Integrated Device Technology], 8S89834AKILF Datasheet - Page 15

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8S89834AKILF

Manufacturer Part Number
8S89834AKILF
Description
Low Skew, 2-to-4 LVCMOS/LVTTL-to-LVPECL/ECL Clock Multiplexer
Manufacturer
IDT [Integrated Device Technology]
Datasheet
ICS8S89834I Data Sheet
Package Outline and Package Dimensions
Package Outline - K Suffix for 16 Lead VFQFN
Table 7. Package Dimensions
Reference Document: JEDEC Publication 95, MO-220
ICS8S89834AKI REVISION A FEBRUARY 4, 2010
There are 3 methods of indicating pin 1 corner
at the back of the VFQFN package are:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type B: Dummy pad between pin 1 and N.
3. Type C: Mouse bite on the paddle (near pin 1)
N
D2 & E2
Symbol
D & E
Index rea
D
CHAMFER
A1
A3
Bottom View w/Type A ID
N
A
All Dimensions in Millimeters
b
& N
L
e
JEDEC Variation: VEED-2/-4
4
E
0.6 x 0.6 max
OPTIONAL
Chamfer 4x
2
1
Minimum
N
0.80
0.18
1.00
0.30
Top View
0
3.00 Basic
0.50 Basic
D
0.25 Ref.
N
16
4
N-1
Maximum
1.00
0.05
0.30
1.80
0.50
Seating Plan
Singulation
Singulation
Sawn
Anvil
or
0. 08
4
A1
C
A
4
Bottom View w/Type B ID
A 3
E 2
C
DD
E2
N & N
(Ref.)
Odd
D
4
L
2
2
1
15
e
E
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
(N
N
D
-1)x e
AA
(R ef.)
D2
4
N-1
D2
2
N
1
2
N & N
Even
(Ref.)
e
D
Thermal
2
Base
If N & N
are Even
(N -1)x e
b
RADIUS
Bottom View w/Type C ID
(Typ.)
E
E
(Re f.)
D
©2010 Integrated Device Technology, Inc.
4
1
E
2
N
N-1

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