8S89834AKILF IDT [Integrated Device Technology], 8S89834AKILF Datasheet - Page 10

• Manufacturer Part Number: 8S89834AKILF
• Description: Low Skew, 2-to-4 LVCMOS/LVTTL-to-LVPECL/ECL Clock Multiplexer
• Manufacturer: IDT [Integrated Device Technology]

ICS8S89834I Data Sheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
Figure 3A. 3.3V LVPECL Output Termination
ICS8S89834AKI REVISION A FEBRUARY 4, 2010
RTT =
((V
3.3V
OH
LVPECL
+ V
OL
) / (V
1
CC
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
* Z
R1
50Ω
o
RTT
R2
50Ω
V
+
_
CC
3.3V
- 2V
Input
10
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 3B. 3.3V LVPECL Output Termination
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
3.3V
LVPECL
Z
Z
o
o
= 50Ω
= 50Ω
R3
125Ω
©2010 Integrated Device Technology, Inc.
R1
84Ω
3.3V
R4
125Ω
R2
84Ω
+
_
3.3V
Input