CYUSB3014 CYPRESS [Cypress Semiconductor], CYUSB3014 Datasheet - Page 22

• Manufacturer Part Number: CYUSB3014
• Description: EZ-USB FX3 SuperSpeed USB Controller UART support up to 4 Mbps
• Manufacturer: CYPRESS [Cypress Semiconductor]

Synchronous Slave FIFO Write Sequence Description
■
■
■
■
■
The same sequence of events is also shown for burst write
Note: Forthe burst mode, SLWR# and SLCS# are left asserted
for the entire duration of writing all the required data values. In
this burst write mode, after the SLWR# is asserted, the data on
Table 10. Synchronous Slave FIFO Parameters
.
Document Number 001-52136 Rev. *H
Note
FREQ
tCYC
tCH
tCL
tRDS
tRDH
tWRS
tWRH
tCO
tDS
tDH
tAS
tAH
tOELZ
tCFLG
tOEZ
tPES
tPEH
tCDH
Note Three-cycle latency from ADDR to DATA/FLAGS
5. All parameters guaranteed by design and validated through characterization.
FIFO address is stable and the signal SLCS# is asserted
External master/peripheral outputs the data onto the data bus
SLWR# is asserted
While the SLWR# is asserted, data is written to the FIFO and
on the rising edge of gthe PCLK, the FIFO pointer is incre-
mented
The FIFO flog is updated after a delay of t
edge of the clock
Parameter
Interface clock frequency
Clock period
Clock high time
Clock low time
SLRD# to CLK setup time
SLRD# to CLK hold time
SLWR# to CLK setup time
SLWR# to CLK hold time
Clock to valid data
Data input setup time
CLK to data input hold
Address to CLK setup time
CLK to address hold time
SLOE# to data low-Z
CLK to flag output propagation delay
SLOE# deassert to Data Hi Z
PKTEND# to CLK setup
CLK to PKTEND# hold
CLK to data output hold
WFLG
from the rising
PRELIMINARY
[5]
Description
the FIFO data bus is written to the FIFO on every rising edge of
PCLK. The FIFO pointer is updated on each rising edge of PCLK.
Short Packet: A short packet can be committed to the USB host
by using the PKTEND#. The external device/processor should
be designed to assert the PKTEND# along with the last word of
data and SLWR# pulse corresponding to the last word. The
FIFOADDR lines have to be held constant during the PKTEND#
assertion.
Zero Length Packet: The external device/processor can signal a
Zero Length Packet (ZLP) to EZ-USB FX3, simply by asserting
PKTEND#, without asserting SLWR#. SLCS# and address must
be driven as shown in the above timing diagram.
FLAG Usage: The FLAG signals are monitored by the external
processor for flow control. FLAG signals are outputs from
EZ-USB FX3 that may be configured to show empty/full/partial
status for a dedicated thread or the current thread being
addressed.
Min
0.5
0.5
0.5
0.5
0.5
10
–
4
4
2
2
–
2
2
0
–
–
2
2
CYUSB3014
Max
100
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Units
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