CYUSB3014 CYPRESS [Cypress Semiconductor], CYUSB3014 Datasheet - Page 18

• Manufacturer Part Number: CYUSB3014
• Description: EZ-USB FX3 SuperSpeed USB Controller UART support up to 4 Mbps
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 9. GPIF II Timing in Asynchronous Mode
Note The following parameters assume one state transition
Document Number 001-52136 Rev. *H
Note
tDS
tDH
tAS
tAH
tCTLassert
tCTLdeassert
tCTLassert_DQassert
tCTLdeassert_DQassert
tCTLassert_DQdeassert
tCTLdeassert_DQdeassert
tCTLassert_DQlatch
tCTLdeassert_DQlatch
tCTLassert_DQlatchDDR
tCTLdeassert_DQlatchDDR
tGRANULARITY
tAA
tDO
4. All parameters guaranteed by design and validated through characterization.
Parameter
CTL deasserted pulse width for CTL inputs that
Data In to DLE setup time. Valid in DDR async
also.
Data In to DLE hold time. Valid in DDR async
mode.
Address In to ALE setup time
Address In to ALE hold time
CTL I/O asserted width for CTRL inputs without
DQ input association and for outputs.
CTL I/O deasserted width for CTRL inputs
without DQ input association and for outputs.
CTL asserted pulse width for CTL inputs that
signify DQ inputs valid at the asserting edge but
do not employ in-built latches (ALE/DLE) for
those DQ inputs.
CTL deasserted pulse width for CTL inputs that
signify DQ input valid at the asserting edge but
do not employ in-built latches (ALE/DLE) for
those DQ inputs.
CTL asserted pulse width for CTL inputs that
signify DQ inputs valid at the de-asserting edge
but do not employ in-built latches (ALE/DLE) for
those DQ inputs.
signify DQ inputs valid at the deasserting edge
but do not employ in-built latches (ALE/DLE) for
those DQ inputs.
CTL asserted pulse width for CTL inputs that
employ in-built latches (ALE/DLE) to latch the
DQ inputs. In this non_DDR case, in-built
latches always close at the de-asserting edge.
CTL deasserted pulse width for CTL inputs that
employ in-built latches (ALE/DLE) to latch the
DQ inputs. In this non-DDR case, in-built
latches always close at the de-asserting edge.
CTL asserted pulse width for CTL inputs that
employ in-built latches (DLE) to latch the DQ
inputs in DDR mode.
CTL deasserted pulse width for CTL inputs that
employ in-built latches (DLE) to latch the DQ
inputs in DDR mode.
Granularity of tCTLassert/tCTLdeassert for all
outputs
DQ/CTL input to DQ output time when DQ
change or CTL change needs to be detected
and affects internal updates of input and output
DQ lines.
CTL to data out when the CTL change merely
enables the output flop update whose data was
already established.
PRELIMINARY
[4]
Description
Min
2.3
2.3
20
20
10
10
10
2
2
7
7
7
7
7
5
–
–
Max
30
25
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
At 200 MHz internal
clock
CYUSB3014
Page 18 of 38
Notes
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