AMD-762JLC AMD [Advanced Micro Devices], AMD-762JLC Datasheet - Page 38

• Manufacturer Part Number: AMD-762JLC
• Description: System Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD-762™ System Controller Data Sheet
26
T h e p ro c e s s o r a n d t h e A M D -7 6 2 s y s t e m c o n t r o l l e r
communicate power-state transitions through the AMD Athlon
system bus connect/disconnect protocol and special cycles
(masked writes to a defined AMD Athlon system bus address
with specific data encoding). In general, the processor initiates
a request for a disconnect with a special cycle, and the
AMD-762 system controller may or may not actually disconnect
the processor with the connect/disconnect protocol. The
A M D -7 6 2 s y s t e m c o n t ro l l e r p e r fo r m s t h e re q u e s t e d
connect/disconnect as part of the process of entering and
exiting certain ACPI states. The following two special cycles
are of interest:
n Halt—Generated
n Stop Grant—Generated by the AMD Athlon processors in
Halt special cycles are generally considered part of an ACPI
state definition (C1). STPCLK#, however, can be asserted at
random times while the processor is in the full-running state
(C0) to conserve power (clock throttling).
response to executing a HALT instruction. The AMD-762
system controller forwards the Halt special cycle to the PCI
bus but does not perform any further power management
for Halt conditions. The processor buses remain connected
and the memory is not placed in self-refresh mode.
response to assertion of STPCLK#. When the AMD-762
system controller receives a Stop Grant from the processor,
it waits for a Stop Grant from the second processor (if
installed), then it sends a Stop Grant special cycle on the
PCI bus. The AMD-762 system controller initiates the
following sequence of actions if the Stop Grant disconnect
bit is set (Dev 0:F0:0x60):
A. Disables PCI/AGP arbitration and waits for all queues to
B. Completes the AMD Athlon system bus cycles. The
C. The Southbridge decodes the special cycle and enters the
memory to be empty (including refresh requests).
AMD-762
AMD Athlon system bus disconnect to the processors,
and causes the memory to enter self-refresh.
appropriate power state. The Southbridge can then
assert DCSTOP#.
Preliminary Information
Functional Operation
system
by
the
controller
AMD Athlon
then
24416C—December 2001
processors
initiates
Chapter 2
an
in