AMD-762JLC AMD [Advanced Micro Devices], AMD-762JLC Datasheet - Page 28

• Manufacturer Part Number: AMD-762JLC
• Description: System Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD-762™ System Controller Data Sheet
2.3.1
2.3.2
Legacy Mode—Single
PCI Bus Southbridge
16
Memory Coherency
PCI Arbitration
The AMD-762 system controller assures that all data accesses
remain coherent:
• All PCI/AGP accesses not in the GART range generate
• The GART range is by definition not cacheable. As a result,
• Processor accesses to addresses mapped by the GART range
The AMD-762 system controller contains arbitration logic that
allocates ownership of the PCI bus among itself on behalf of
the processors, the Southbridge, and other PCI initiators.
The AMD-762 supports up to seven bus grant pins and a
dedicated grant pin for the Southbridge when operating in
legacy mode. The request/grant pairs used depend on the
system configuration supported as described in the following
sections.
The legacy mode implies a standard system configuration
where the PCI bus typically operates at 33 MHz with a common
Southbridge such as the AMD-766 peripheral bus controller.
All PCI agents connect to this PCI bus segment and their
request grant pairs are connected to the AMD-762 system
controller’s REQ[6:0]# and GNT[6:0]# pins, while the
Southbridge connects to the SBREQ#/SBGNT# pins.
The SBREQ#/SBGNT# pins are treated differently than the
standard request/grant pairs as is required for legacy ISA DMA
cycles. To avoid potential deadlock conditions, the AMD-762
system controller allows the SBREQ# to be asserted for
extended periods of time. Bus masters using the REQ[6:0]# and
GNT[6:0]# signals are preempted when another requestor
processor probes assuring that reads receive only the latest
version of the data and that writes update only the latest
version of the data. Writes are always performed in order.
all PCI/AGP accesses that are in the GART range are
subject to non-cacheable ordering rules—that is, they do not
generate probes to the processor, writes are performed in
order, and reads receive the results of all earlier writes.
can either use the GART for the final address translation or
map the addresses through its page tables as a non-
cacheable memory type.
Preliminary Information
Functional Operation
24416C—December 2001
Chapter 2