HS9-82C85RH-8 INTERSIL [Intersil Corporation], HS9-82C85RH-8 Datasheet - Page 2

• Manufacturer Part Number: HS9-82C85RH-8
• Description: Radiation Hardened CMOS Static Clock Controller/Generator
• Manufacturer: INTERSIL [Intersil Corporation]

Pinouts
Pin Descriptions
S2/STOP
START
PIN
EFI
F/C
X1
X2
S0
S1
SLO/FST
NUMBER
CSYNC
READY
24 LEAD CERAMIC DUAL-IN-LINE
START
CLK50
METAL SEAL PACKAGE (SBDIP)
PCLK
AEN1
AEN2
RDY1
RDY2
GND
CLK
PIN
23
22
20
19
11
13
14
15
MIL-STD-1835 CDIP2-T24
10
11
12
1
2
3
4
5
6
7
8
9
TOP VIEW
TYPE
O
I
I
I
I
I
I
I
2
CRYSTAL CONNECTIONS: X1 and X2 are the crystal oscillator connections. The crystal frequency
must be three times the maximum desired processor clock frequency. X1 is the oscillator circuit input and
X2 is the output of the oscillator circuit.
EXTERNAL FREQUENCY IN: When F/C is HIGH, CLK is generated from the EFI input signal. This input
signal should be a square wave with a frequency of three times the maximum desired CLK output
frequency.
FREQUENCY/CRYSTAL SELECT: F/C selects either the crystal oscillator or the EFI input as the main
frequency source. When F/C is LOW, the HS-82C85RH clocks are derived from the crystal oscillator
circuit. When F/C is HIGH, CLK is generated from the EFI input. F/C cannot be dynamically switched
during normal operation.
A low-to-high transition on START will restart the CLK, CLK50 and PCLK outputs after the appropriate
restart sequence is completed.
When in the crystal mode (F/C LOW) with the oscillator stopped, the oscillator will be restarted when a
Start command is received. The CLK, CLK50 and PCLK outputs will start after the oscillator input signal
(X1) reaches the Schmitt trigger input threshold and an 8K internal counter reaches terminal count. If F/C
is HIGH (EFI mode), CLK, CLK50 and PCLK will restart within 3 EFI cycles after START is recognized.
The HS-82C85RH will restart in the same mode (SLO/FST) in which it stopped. A high level on START
disables the STOP mode.
S2/STOP, S1, S0 are used to stop the HS-82C85RH clock outputs (CLK, CLK50, PCLK) and are sampled
by the rising edge of CLK. CLK, CLK50 and PCLK are stopped by S2/STOP, S1, S0 being in the LHH
state on the low-to-high transition of CLK. This LHH state must follow a passive HHH state occurring on
the previous low-to-high CLK transition. CLK and CLK50 stop in the high state. PCLK stops in it’s current
state (high or low).
When in the crystal mode (F/C) low and a STOP command is issued, the HS-82C85RH oscillator will stop
along with the CLK, CLK50 and PCLK outputs. When in the EFI mode, only the CLK, CLK50 and PCLK
outputs will be halted. The oscillator circuit if operational, will continue to run. The oscillator and/or clock
is restarted by the START input signal going true (HIGH) or the reset input (RES) going low.
24
23
22
21
20
19
18
17
16
15
14
13
V
X1
X2
ASYNC
EFI
F/C
OSC
RES
RESET
S2/STOP
S1
S0
DD
HS-82C85RH
DESCRIPTION
SLO/FST
CSYNC
READY
START
CLK50
PCLK
AEN1
AEN2
RDY1
RDY2
GND
CLK
FLATPACK PACKAGE (FLATPACK)
24 LEAD CERAMIC METAL SEAL
MIL-STD-1835 CDFP4-F24
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
X1
X2
ASYNC
EFI
F/C
OSC
RES
RESET
S2/STOP
S1
S0
V
DD