HS9-82C85RH-8 INTERSIL [Intersil Corporation], HS9-82C85RH-8 Datasheet - Page 14

• Manufacturer Part Number: HS9-82C85RH-8
• Description: Radiation Hardened CMOS Static Clock Controller/Generator
• Manufacturer: INTERSIL [Intersil Corporation]

Internal logic requires that the SLO/FST pin be held low for
at least 195 oscillator or EFI clock pulses before the SLOW
mode command is recognized. This requirement eliminates
unwanted FAST-to-SLOW mode frequency changes which
could be caused by glitches or noise spikes.
To guarantee FAST mode recognition, the SLO/FST pin
must be held high for at least 3 OSC or EFI pulses. The
HS-82C85RH will begin FAST mode operation on the next
PCLK edge after FAST command recognition. Proper CLK
and CLK50 phase relationships are maintained and
minimum pulse width specifications are met.
FAST-to-SLOW or SLOW-to-FAST mode changes will occur
on the next rising or falling edge of PCLK. It is important to
remember that the transition time for operating frequency
changes, which are dependent upon PCLK, will vary with the
HS-82C85RH oscillator or EFI frequency.
Slow/Fast Mode Control
The HS-82C55ARH programmable peripheral interface can
be used to provide slow/fast mode control by connecting one
of the port pins directly to the SLO/FST pin (see Figure 21).
With the port pin configured as an output, software control of
the SLO/FST pin is provided by simply writing a logical one
(FAST mode) or logical zero (SLOW Mode) to the
corresponding port. PORT C is well-suited for this function
due to its bit set and reset capabilities.
Alternate Operating Modes
Using alternate modes of operation (slow, stop-clock, stop-
oscillator) will reduce the average system operating power
dissipation in a static CMOS system (see Table 2). This does
not mean that system speed or throughput must be reduced.
When used appropriately, the slow, stop-clock, stop-
oscillator modes can make your design more power-efficient
while maintaining maximum system performance.
Oscillator
The oscillator circuit of the HS-82C85RH is designed
primarily for use with an external parallel resonant,
fundamental mode crystal from which the basic operating
frequency is derived. The crystal frequency must be three
times the required CPU clock. X1 and X2 are the two crystal
FIGURE 21. SLOW/FAST MODE CONTROL USING
CONTROLLER
HS-82C85RH
GENERATOR
CLOCK
SLO/FST
CLK
HS-82C55RH PERIPHERAL INTERFACE
PERIPHERAL
PC0
HS-82C55RH
INTERFACE
14
CLK
D0 - 8
HS-80C86RH
PROCESSOR
HS-82C85RH
input connections. The output of the oscillator is buffered
and available at the OSC output (pin 18) for generation of
other system timing signals.
NOTE: All measurements taken at room temperature, VDD = +5.0V.
Power supply current levels will be dependent upon system
configuration and frequency of operation.
For the most stable operation of the oscillator (OSC) output
circuit, two capacitors (C1 = C2) are recommended.
Capacitors C1 and C2 are chosen such that their combined
capacitance matches the load capacitance as specified by
the crystal manufacturer. This insures operation within the
frequency tolerance specified by the crystal manufacturer.
The crystal/capacitor configuration and the formula used to
determine the capacitor values are shown in Figure 22.
Crystal Specifications are shown in Table 3. For additional
information on crystal operation, see Intersil publication Tech
Brief 47.
CPU Frequency
XTAL Frequency
IDD
HS-80C86RH
HS-82C85RH
HS-82C08RH
82C82
HS-82C54RH
HS-82C55ARH
74HCXX + Other
HS-65262RH
HS-6617RH
TABLE 2. TYPICAL SYSTEM POWER SUPPLY CURRENT
2.4MHz - 15MHz
CT
FOR STATIC CMOS OPERATING MODES
FIGURE 22. CRYSTAL CONNECTION
CRYSTAL
=
--------------------- - (Including stray capacitance)
C1
C1 C2
+
943
24.7mA
15MHz
1.0mA
1.7mA
2.9mA
4.0mA
6.3mA
C2
FAST
5MHz
50mA
3.2 A
A
C
C
915.0 A
110.0 A
16.9mA
1
2
10.0 A
50.0 A
52.5 A
15MHz
SLOW
2.5mA
6.5mA
20kHz
1.2 A
CLOCK
14.1mA
X1
X2
15MHz
90.0 A
10.0 A
12.0 A
STOP-
250 A
1.0 A
1.0 A
1.0 A
1.0 A
DC
24.4 A
90.0 A
10.0 A
12.0 A
STOP-
250 A
1.0 A
1.0 A
1.0 A
1.0 A
OSC
DC
DC