HS9-65647RH INTERSIL [Intersil Corporation], HS9-65647RH Datasheet
HS9-65647RH
Related parts for HS9-65647RH
HS9-65647RH Summary of contents
Page 1
... Ordering Information PART NUMBER HS1-65647RH-Q HS1-65647RH-8 HS1-65647RH/Proto HS1-65647RH/Sample HS9-65647RH-Q HS9-65647RH-8 HS9-65647RH/Proto HS9-65647RH/Sample HS9A-65647RH-Q CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | http://www.intersil.com or 407-727-9207 Copyright HS-65647RH Functional Diagram AI ROW Errors/Bit-Day ...
Page 2
... DQ2 13 16 GND A12 DQ0 DQ1 DQ2 GND DQ0 DQ1 DQ2 GND HS-65647RH HS9-65647RH 28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) NC VDD A12 A11 A10 DQ7 DQ0 DQ1 DQ6 DQ2 ...
Page 3
Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Address Access Time TAVQV Output Enable Access Time TGLQV Chip Enable Access Time TE1LQV TE2HQV Write Recovery Time TWHAX TE1HAX TE2LAX Chip Enable to End-of-Write TE1LE1H TE2HE2L Address Setup Time TAVWL TAVE1L ...
Page 5
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL Write Enable High to Out- TWHQX put ON Chip Enable to Output ON TE1LQX TE2HQX Output Enable to Output TGLQX ON Chip Enable to Output in TE1HQZ High Z TE2LQZ Output Disable ...
Page 6
TABLE 5. BURN-IN DELTA PARAMETERS (+25 PARAMETER Standby Supply Current High Impedance Output Leakage Current Input Leakage Current Low Level Output Voltage Output High Voltage CONFORMANCE MIL-STD-883 GROUP METHOD Initial Test 100% 5004 Interim Test 100% 5004 PDA 100% 5004 ...
Page 7
Intersil Space Level Product Flow -Q Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 ...
Page 8
Intersil Space Level Product Flow -8 GAMMA Radiation Verification (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects Periodic- Wire Bond Pull Monitor, Method 2011 Periodic- Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition B ...
Page 9
Timing Waveforms TAVAX ADDRESS 1 A TAVQV Q FIGURE 1. READ CYCLE HIGH LOW A TAVQV E1 TE1LQV TE1LQX E2 TE2HQV TE2HQX G TGLQX Q A TAVWL HS-65647RH ADDRESS 2 ...
Page 10
Timing Waveforms (Continued) A TAVE1L FIGURE 4. WRITE CYCLE II: EARLY WRITE - CONTROLLED TAVE2H FIGURE 5. WRITE CYCLE III: EARLY WRITE - CONTROLLED BY E2 HS-65647RH TAVAX TE1LE1H ...
Page 11
Performance Curves HS-65647RH TYPICAL PERFORMANCE CHARACTERISTICS 200 400 600 800 TOTAL DOSE (KRAD) FIGURE ...
Page 12
Burn-In Circuits HS-65647RH 28 LEAD FLATPACK AND CERAMIC DIP F13 A12 ...
Page 13
Irradiation Circuit HS-65647RH ( TSOS4 SRAM) 28 LEAD CERAMIC DIP NOTES: 1. VDD = 5.5V 0. 10k 10% 2. Group E sample size is two die/wafer. Test Patterns MARCH (II)PATTERN After a background of zeros is ...
Page 14
Metallization Topology DIE DIMENSIONS: 313 x 291 x 21 1mils METALLIZATION: Type: Al/Si/Cu Å Å Metal 1 Thickness: 7500 2k Å Å Metal 2 Thickness: 10k k Metallization Mask Layout VSS VDD HS-65647RH GLASSIVATION: Type: SiO 2 Å Å Thickness: ...
Page 15
Packaging e PIN NO AREA - 0.004 0.036 - SEATING AND BASE PLANE c1 LEAD FINISH BASE (c) METAL b1 M ...
Page 16
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, ...