HYS64T256020HU-3-A QIMONDA [Qimonda AG], HYS64T256020HU-3-A Datasheet - Page 32
![no-image](/images/no-image-200.jpg)
HYS64T256020HU-3-A
Manufacturer Part Number
HYS64T256020HU-3-A
Description
240-Pin Unbuffered DDR2 SDRAM Modules
Manufacturer
QIMONDA [Qimonda AG]
Datasheet
1.HYS64T256020HU-3-A.pdf
(61 pages)
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3.3.3
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Rev. 1.32, 2006-09
03062006-5RK8-1X8J
Symbol
t
t
t
t
t
t
t
t
Symbol
t
t
t
t
t
t
t
t
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
the ODT resistance is fully on. Both are measure from
Both are measured from
the ODT resistance is fully on. Both are measure from
Both are measured from
Parameter / Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
Parameter / Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
ODT AC Electrical Characteristics
t
t
AOFD
AOFD
.
.
ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400
ODT AC Characteristics and Operating Conditions for DDR2-667
t
t
AOND
AOND
.
.
Values
Min.
2
t
t
2.5
t
t
3
8
Values
Min.
2
t
t
2.5
t
t
3
8
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
32
+ 2 ns
+ 2 ns
+ 2 ns
+ 2 ns
Max.
2
t
2
t
2.5
—
Max.
2
t
2
t
2.5
—
2.5
—
2.5
—
AC.MAX
AC.MAX
AC.MAX
AC.MAX
t
t
CK +
CK +
t
t
CK +
CK +
t
t
+ 0.7 ns
AC.MAX
+ 0.6 ns
+ 1 ns
AC.MAX
+ 0.6 ns
Unbuffered DDR2 SDRAM Modules
t
t
HYS[64/72]T256xxxHU–[3/…/5]–A
AC.MAX
AC.MAX
+ 1 ns
+ 1 ns
+ 1 ns
+ 1 ns
Internet Data Sheet
Unit
t
ns
ns
t
ns
ns
t
t
Unit
t
ns
ns
t
ns
ns
t
t
CK
CK
CK
CK
CK
CK
CK
CK
TABLE 20
TABLE 21
Note
Note
1)
2)
1)
2)
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