HYS64T128920HU QIMONDA [Qimonda AG], HYS64T128920HU Datasheet - Page 32

• Manufacturer Part Number: HYS64T128920HU
• Description: 240-Pin Unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

3.4
Chapter contains current tables for each of the product types and the definitions of the various currents.
•
•
•
•
•
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
Parameter
Operating Current 0
One bank Active - Precharge;
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge;
t
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Data bus inputs are FLOATING.
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
SWITCHING; Data Bus inputs are SWITCHING;
Active Power-Down Current
All banks open;
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
All banks open; t
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
bus inputs are SWITCHING;
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
t
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
t
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
RCD
RAS
RP
RAS
CK
Table 22 “IDD Measurement Conditions” on Page 32
Table 23 “Definitions for IDD” on Page 33
Table 24 “IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3–A” on Page 34
Table 25 “IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3S–A” on Page 35
Table 26 “IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3.7–A” on Page 36
=
=
=
=
=
t
t
RPMIN
CK.MIN
t
t
t
RAS.MAX
RAS.MAX.
RCD.MIN
; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
., Refresh command every
, AL = 0, CL = CL
,
,
t
t
t
RP
CK
CK
RP
=
=
=
=
Currents Specifications and Conditions
t
t
t
t
RP.MIN
CK.MIN
CK.MIN
RP.MAX
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
I
t
OUT
CK
MIN
=
= 0mA.
; CKE is HIGH, CS is HIGH between valid commands. Address and
t
CK.MIN
I
OUT
t
RFC
t
,
CK
t
t
= 0 mA, BL = 4,
RC
CK
=
=
t
=
=
t
RFC.MIN
CK.MIN
t
t
RC.MIN
CK.MIN
I
OUT
; Other control and address inputs are SWITCHING,
interval, CKE is HIGH, CS is HIGH between valid
,
; Other control and address inputs are STABLE,
= 0 mA.
t
RAS
=
t
CK
t
32
RAS.MIN
=
t
MIN
CK.MIN
MIN
, CKE is HIGH, CS is HIGH between
;
;
t
t
CK
CK
,
t
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
RC
=
=
t
t
CKMIN
=
CK.MIN
t
MIN
RC.MIN
;
;
;
t
t
RAS
CK
,
Unbuffered DDR2 SDRAM Modules
t
=
RAS
=
t
CK.MIN
t
RASMAX
=
I
DD
t
RAS.MIN
;
Measurement Conditions
;
,
Internet Data Sheet
Symbol Note
I
I
I
I
I
I
I
I
I
I
I
DD0
DD1
DD2N
DD2P
DD2Q
DD3N
DD3P(0)
DD3P(1)
DD4R
DD4W
DD5B
TABLE 22
1)2)3)4)5)
6)
6)