HYS64T128920HU QIMONDA [Qimonda AG], HYS64T128920HU Datasheet - Page 30

• Manufacturer Part Number: HYS64T128920HU
• Description: 240-Pin Unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

13) The
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
15) 0 °C≤
16) 85 °C <
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The
19) The maximum limit for the
20) WR must be programmed to fulfill the minimum requirement for the
21) Minimum
22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
(
parameters are verified by design and characterization, but not subject to production test.
and 95 °C.
Compliant Products” on Page
performance (bus turnaround) degrades accordingly.
up to the next integer value.
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
down mode” (MR, A12 = “0”) a fast power-down exit timing
power-down exit timing
t
HZ,
t
t
t
HZ
RPST
RRD
T
,
CASE
T
t
RPST
), or begins driving (
timing parameter depends on the page size of the DRAM organization. See
CASE
t
WTR
≤ 85 °C
and
≤ 95 °C
is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
t
LZ
,
t
RPRE
t
XARDS
t
parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
WPST
t
t
DAL
LZ,
has to be satisfied.
t
parameter is not a device limit. The device operates with a greater value for this parameter, but system
5.
= WR + (
RPRE
).
t
HZ
t
RP
and
/
t
CK
t
LZ
). For each of the terms, if not already an integer, round to the next highest integer.
transitions occur in the same access time windows as valid data transitions.These
t
XARD
30
can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
t
WR
timing parameter, where
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Table 4 “Ordering Information for RoHS
Unbuffered DDR2 SDRAM Modules
WR
MIN
[cycles] =
Internet Data Sheet
t
WR
(ns)/
t
CK
(ns) rounded
t
CK