HYS64T128920HU QIMONDA [Qimonda AG], HYS64T128920HU Datasheet - Page 22

• Manufacturer Part Number: HYS64T128920HU
• Description: 240-Pin Unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

6) Inputs are not recognized as valid until
7) The output timing reference voltage level is
8) New units, ‘
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
12) Input waveform timing
13) If
14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
15) Input waveform timing
16)
17)
18)
19)
20)
21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
22) Input waveform timing is referenced from the input signal crossing at the
23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
24) Input waveform timing is referenced from the input signal crossing at the
25)
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
ps and
t
= - 900 ps – 293 ps = – 1193 ps and
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations).
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between
Figure
((L/U/R)DQS / DQS) crossing.
the input signal crossing at the
at the
V
t
which specifies when the device output is no longer driving (
t
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
t
It is used in conjunction with t
following equation;
minimum of the actual instantaneous clock low time.
t
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
t
the max column. {The less half-pulse width distortion present, the larger the
Examples: 1) If the system provides
provides
The spec values are not affected by the amount of clock jitter applied (i.e.
crossing. That is, these parameters should be met whether clock jitter is present or not.
to the device under test. See
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
to the device under test. See
t
(
driving (
calculation is consistent.
DQSCK.MAX(DERATED)
HZ
DQSQ
HP
QHS
QH
RPST
t
RPST
IH.DC.MIN
t
DS
and
is the minimum of the absolute half period of the actual input clock.
=
accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual
or
: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
end point and
), or begins driving (
t
HP
V
t
4.
t
IL.DC
t
ERR(6- 10PER).MAX
t
LZ
DH
RPRE
. See
–
t
HP
transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
t
is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
t
QHS
CK.AVG
level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between
of 1420 ps into a DDR2–667 SDRAM, the DRAM provides
t
) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
CK
Figure
, where:
‘ is used for both concepts. Example:
‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘
=
t
t
HP
RPRE
t
DQSCK.MAX
t
4.
t
= MIN (
DS
= + 293 ps, then
DH
t
HP
begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
t
with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the
RPRE
with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
is the minimum of the absolute half period of the actual input clock; and
QHS
Figure
Figure
t
).
CH.ABS
–
V
Figure 3
IH.DC
t
to derive the DRAM output timing
ERR(6-10PER).MIN
t
HP
,
t
5.
5.
level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
LZ.DQ.MAX(DERATED)
t
CL.ABS
V
of 1315 ps into a DDR2–667 SDRAM, the DRAM provides
t
REF
DQSCK.MIN(DERATED)
shows a method to calculate these points when the device is no longer driving (
V
), where,
stabilizes. During the period before
TT
.
= 400 ps + 272 ps = + 672 ps. Similarly,
t
t
XP
CH.ABS
= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
t
CK.AVG
=
t
is the minimum of the actual instantaneous clock high time;
t
HZ
DQSCK.MIN
), or begins driving (
+
22
t
ERR.2PER(Min)
t
QH
. The value to be used for
t
–
HP
t
V
V
QH
t
IH.AC
IL.DC
ERR(6-10PER).MAX
is an input parameter but not an input specification parameter.
t
JIT.PER
of 1080 ps minimum.
t
QH
level for a rising signal and
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
level for a rising signal and
.
value is; and the larger the valid data eye will be.}
V
,
REF
t
t
CK.AVG
JIT.CC
t
LZ
stabilizes, CKE = 0.2 x
) .
, etc.), as these are relative to the clock signal
t
‘ represents the actual
= – 400 ps – 293 ps = – 693 ps and
LZ.DQ
Unbuffered DDR2 SDRAM Modules
for DDR2–667 derates to
t
V
t
QH
QH
IL.AC
t
QHS
t
calculation is determined by the
ERR(6-10per)
of 975 ps minimum. 2) If the system
level to the differential data strobe
is the specification value under
V
V
IH.DC
IL.AC
V
V
il(DC)MAX
DDQ
of the input clock. (output
for a falling signal applied
for a falling signal applied
t
Internet Data Sheet
CK.AVG
t
HP
t
is recognized as low.
ERR(6-10PER).MIN
at the input is
V
and
IL.DC.MAX
of the input clock
t
LZ.DQ.MIN(DERATED)
t
t
t
RPST
JIT.PER
CL.ABS
V
ih(DC)MIN
), or begins
V
and
IH.AC
,
is the
t
= – 272
JIT.CC
. See
level
,