HYS64D16301GU INFINEON [Infineon Technologies AG], HYS64D16301GU Datasheet - Page 27

• Manufacturer Part Number: HYS64D16301GU
• Description: 184-Pin Unbuffered Dual-In-Line Memory Modules
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 16
Parameter
DQS falling edge to CK setup time (write
cycle)
DQS falling edge hold time from CK (write
cycle)
Mode register set command cycle time
Write preamble setup time
Write postamble
Write preamble
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command
period
Auto-refresh to Active/Auto-refresh
command period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
1) 0 C
2) Input slew rate
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
Data Sheet
level for signals other than CK/CK, is
T
A
70 C
AC Timing - Absolute Specifications –6/–5 (cont’d)
; V
1 V/ns for DDR400, DDR333
DDQ
= 2.5 V 0.2 V,
V
V
REF
V
DD
REF
. CK/CK slew rate are
= +2.5 V 0.2 V (DDR333);
stabilizes.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DSS
DSH
MRD
WPRES
WPST
WPRE
IS
IH
RPRE
RPST
RAS
RC
RFC
RCD
RP
RAP
RRD
WR
DAL
WTR
XSNR
XSRD
REFI
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Min.
0.2
0.2
2
0
0.40
0.25
0.75
0.8
0.75
0.8
0.9
0.40
42
60
72
18
18
18
12
15
1
75
200
—
27
DDR333
–6
Max.
—
—
—
—
0.60
—
—
—
—
—
1.1
0.60
70E+3 40
—
—
—
—
—
—
—
—
—
—
7.8
1.0 V/ns.
V
DDQ
Unbuffered DDR SDRAM Modules
Min.
0.2
0.2
2
0
0.40
0.25
0.6
NA
0.6
NA
0.9
0.40
55
65
15
15
15
10
15
1
75
200
—
= 2.6 V 0.1 V,
DDR400B
–5
Max.
—
—
—
—
0.60
—
—
—
1.1
0.60
70E+3 ns
—
—
—
—
—
—
—
—
—
—
7.8
V
Electrical Characteristics
DD
Unit Note/
t
t
t
ns
t
t
ns
ns
ns
ns
t
t
ns
ns
ns
ns
ns
ns
ns
t
t
ns
t
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
s
= +2.6 V 0.1 V (DDR400)
Test Condition
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)8)
2)3)4)5)9)
2)3)4)5)
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)12)
V1.1, 2003-07
V
TT
1)
.