HYS64D16301GU INFINEON [Infineon Technologies AG], HYS64D16301GU Datasheet - Page 25

• Manufacturer Part Number: HYS64D16301GU
• Description: 184-Pin Unbuffered Dual-In-Line Memory Modules
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 15
Parameter
Address and control input
setup time
Address and control input
hold time
Read preamble
Read preamble setup time
Read postamble
Active to Precharge
command
Active to Active/Auto-
refresh command period
Auto-refresh to Active/Auto-
refresh command period
Active to Read or Write
delay
Precharge command period
Active to Autoprecharge
delay
Active bank A to Active
bank B command
Write recovery time
Auto precharge write
recovery + precharge time
Internal write to read
command delay
Exit self-refresh to non-read
command
Exit self-refresh to read
command
Average Periodic Refresh
Interval
1) 0 C
2) Input slew rate
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
Data Sheet
level for signals other than CK/CK, is
T
A
AC Timing - Absolute Specifications –8/–7/–7F (cont’d)
70 C;
1 V/ns for DDR400, DDR333, DDR266, and = 1 V/ns for DDR200
V
DDQ
= 2.5 V 0.2 V,
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IS
IH
RPRE
RPRE1.5
RPRES
RPST
RAS
RC
RFC
RCD
RP
RAP
RRD
WR
DAL
WTR
WTR1.5
XSNR
XSRD
REFI
V
REF
Min.
1.1
1.1
1.1
1.1
0.9
0.9
1.5
0.40
50
70
80
20
20
20
15
15
1
2
80
200
—
V
V
DD
REF
. CK/CK slew rate are
DDR200
= +2.5 V 0.2 V
stabilizes.
–8
Max.
—
—
—
—
1.1
1.1
—
0.60
120
E+3
—
—
—
—
—
—
—
—
—
—
—
7.8
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
(
t
25
Min.
0.9
1.0
0.9
1.0
0.9
NA
NA
0.40
45
65
75
20
20
20
15
15
1
—
75
200
—
wr
/
DDR266A
t
CK
) + (
–7
Max.
—
—
—
—
1.1
0.60
120
E+3
—
—
—
—
—
—
—
—
—
—
—
7.8
1.0 V/ns.
t
rp
/
t
CK
Unbuffered DDR SDRAM Modules
)
Min.
0.9
1.0
0.9
1.0
0.9
NA
NA
0.40
45
60
75
15
15
15
15
15
1
—
75
200
—
DDR266
–7F
Max.
—
—
—
—
1.1
0.60
120
E+3
—
—
—
—
—
—
—
—
—
—
—
7.8
Electrical Characteristics
Unit Note/
ns
ns
ns
ns
t
t
ns
t
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
ns
t
CK
CK
CK
CK
CK
CK
CK
s
Test Condition
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
CL > 1.5
CL = 1.5
2)3)4)5)12)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)13)
CL > 1.5
CL = 1.5
2)3)4)5)
2)3)4)5)
2)3)4)5)14)
V1.1, 2003-07
2)3)4)5)
2)3)4)5)11)
2)3)4)5)
2)3)4)5)
V
TT
1)
.