SSD1820ATR1 ETC1 [List of Unclassifed Manufacturers], SSD1820ATR1 Datasheet - Page 16

• Manufacturer Part Number: SSD1820ATR1
• Description: LCD Segment / Common Driver with Controller CMOS
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

SSD1820A/21
16
HV Buffer Cell (Level Shifter)
voltage output signal to the required driving voltage. The output is
shifted out with an internal FRM clock which comes from the Display
Timing Generator. The voltage levels are given by the level selector
which is synchronized with the internal M signal.
Reset Circuit
initialized only:
HV Buffer Cell works as a level shifter which translates the low
When RES input is low, the chip is initialized to the following:
1. Page address is set to 0
2. Column address is set to 0
3. Display is OFF
4. Display Start Line is set to 0 (GDDRAM page 0, D0)
5. Display Offset is set to 0 (COM0 is mapped to ROW0)
6. 128x64 for SSD1820A / 128x80 for SSD1821
7. Normal/Reverse Display is Normal
8. n-line Inversion Register is 0
9. Entire Display is OFF
10. Power Control Register (VC, VR, VF) is set to (0,0,0)
11. 2X/3X Booster is selected
12. Internal Resistor Ratio register is set to 0H
13. Software Contrast is set to 32
14. LCD Bias Ratio is set to 1/9 for SSD1820A and 1/10 for
15. Normal scan direction of COM outputs
16. Segment remap is disabled (SEG0 display column address 0)
17. Internal oscillator is OFF
18. Test mode is OFF
19. Temperature coefficient is set to PTC0 for SSD1820A and
20. Icon display line is OFF
21. Interface Lock / Unlock register will be clear
When RESET command is issued, the following parameters are
1. Page address is set to 0
2. Column address is set to 0
3. Initial Display Line is set to 0 (point to display RAM page 0, D0)
4. Internal Resistor Ratio register is set to 0H
PTC1 for SSD1821.
SSD1821.
REV 1.4
01/03
SOLOMON