SSD1820ATR1 ETC1 [List of Unclassifed Manufacturers], SSD1820ATR1 Datasheet - Page 12

• Manufacturer Part Number: SSD1820ATR1
• Description: LCD Segment / Common Driver with Controller CMOS
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

SSD1820A/21
12
Command Decoder and Command Interface
command. Data is directed to this module based upon the input of the D/C
pin. If D/C is high, data is written to Graphic Display Data RAM
(GDDRAM). If D/C is low, the input at D
and it will be decoded and written to the corresponding command register.
receives a negative reset pulse of about 1us, all internal circuitry will be
back to its initial status. Refer to Command Description section for more
information.
MPU Parallel 6800-series Interface
W(WR), D/C, E(RD) and CS. R/W(WR) input High indicates a read opera-
tion from the Graphic Display Data RAM (GDDRAM) or the status register.
R/ W(WR) input Low indicates a write operation to Display Data RAM or
Internal Command Registers depending on the status of D/C input. The
E(RD) and CS input serves as data latch signal (clock) when they are high
and low respectively. Refer to Figure 1 of parallel timing characteristics for
Parallel Interface Timing Diagram of 6800-series microprocessors.
the microprocessor, some pipeline processing is internally performed
which requires the insertion of a dummy read before the first actual display
data read. This is shown in Figure 4 below.
MPU Parallel 8080-series interface
W(WR), E(RD), D/C and CS. The CS input serves as data latch signal
(clock) when it is low. Whether it is display data or status register read is
controlled by D/C. R/W(W R) and E(RD) input indicates a write or read
cycle when CS is low. Refer to Figure 2 of parallel timing characteristics for
Parallel Interface Timing Diagram of 8080-series microprocessor.
the first actual display data read.
Graphic Display Data RAM (GDDRAM)
displayed. The size of the RAM is 128 x 65 = 8320bits for SSD1820A; 128
x 81 = 10368bits for SSD1821. Figure 5, 6 are the description of the
GDDRAM address map. For mechanical flexibility, re-mapping on both
The GDDRAM is a bit mapped static RAM holding the bit pattern to be
This module determines whether the input data is interpreted as data or
Reset is of the same function as Power ON Reset (POR). Once RES
The parallel interface consists of 8 bi-directional data pins (D
In order to match the operating frequency of display RAM with that of
The parallel interface consists of 8 bi-directional data pins (D
Similar to 6800-series interface, a dummy read is also required before
R/W(WR)
data bus
E(RD)
REV 1.4
01/03
write column address
N
0
-D
OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER
Figure 4: display data read with the insertion of dummy read
7
is interpreted as a Command
dummy read
Description of Block Diagram Module
0
0
-D
-D
7
7
), R /
), R /
data read1
n
Segment and Common outputs are provided. For vertical scrolling of
display, an internal register storing the display start line can be set to
control the portion of the RAM data to be mapped to the display. Figure
5, 6 show the case in which the display start line register is set at 38H.
MPU Serial 4-wire Interface
C and CS . SDA is shifted into a 8-bit shift register on every rising edge
of SCL in the order of D
clock and the data byte in the shift register is written to the Display Data
RAM or command register in the same clock. No extra clock or com-
mand is required to end the transmission.
MPU Serial 3-wire Interface
used. The Display Data Length instruction is used to indicate that a
specified number display data byte (1-256) are to be transmitted. Next
byte after the display data string is handled as a command.
an out of synchronization in the serial communication, a hardware reset
pulse at RES pin is required to initialize the chip for re-synchronization.
Modes of operation
Data Read
Data Write
Command Read
Command Write
The serial interface consists of serial clock SCK, serial data SDA, D/
Operation is similar to 4-wire serial interface while D/ C is not been
It should be noted that if there is a signal glitch at SCK that causing
data read 2
n + 1
6800 parallel
Yes
Yes
Status only
Yes
7
, D
6
,... D
0
8080 parallel
Yes
Yes
Status only
Yes
. D/C is sampled on every eighth
data read 3
n+2
Serial
No
Yes
No
Yes
SOLOMON