IC42S16100-5T ICSI [Integrated Circuit Solution Inc], IC42S16100-5T Datasheet - Page 17
![no-image](/images/no-image-200.jpg)
IC42S16100-5T
Manufacturer Part Number
IC42S16100-5T
Description
512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
Manufacturer
ICSI [Integrated Circuit Solution Inc]
Datasheet
1.IC42S16100-5T.pdf
(78 pages)
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IC42S16100
CKE RELATED COMMAND TRUTH TABLE
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
Current State
Self-Refresh
Self-Refresh Recovery
Power-Down
Both Banks Idle
Other States
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input
2. The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH. The
3. Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode.
4. The input must be command defined in the operation command table.
minimum setup time (t
Operation
Undefined
Self-Refresh Recovery
Self-Refresh Recovery
Illegal
Illegal
Self-Refresh
Idle State After t
Idle State After t
Illegal
Illegal
Power-Down on the Next Cycle
Power-Down on the Next Cycle
Illegal
Illegal
Clock Suspend Termination on the Next Cycle
Clock Suspend
Undefined
Power-Down Mode Termination, Idle After
That Termination
Power-Down Mode
No Operation
See the Operation Command Table
Bank Active Or Precharge
Auto-Refresh
Mode Register Set
See the Operation Command Table
See the Operation Command Table
See the Operation Command Table
Self-Refresh
See the Operation Command Table
Power-Down Mode
See the Operation Command Table
Clock Suspend on the Next Cycle
Clock Suspend Termination on the Next Cycle
Clock Suspend Termination on the Next Cycle
CKA
(2)
(2)
) required before all commands other than mode termination must be satisfied.
(3)
RC
RC
(2)
Has Elapsed
Has Elapsed
(3)
(2)
(2)
(4)
(1)
(2)
n-1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
CKE
X
H
H
H
H
H
H
H
H
H
X
H
H
H
H
H
H
X
H
H
n
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CS
CS
CS RAS
CS
CS
H
H
H
H
H
X
L
L
L
X
L
L
L
L
L
L
X
X
X
X
X
L
L
L
L
L
L
L
L
X
X
X
X
X
RAS
RAS
RAS CAS
RAS
X
X
H
H
X
X
H
H
X
H
H
X
X
X
X
X
X
H
X
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
CAS
CAS
CAS
CAS WE
X
X
H
X
X
X
H
X
X
H
X
X
X
X
X
X
X
X
H
X
X
H
X
X
X
X
X
L
L
L
L
L
L
L
WE
WE A11 A10 A9-A0
WE
WE
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OP CODE
OP CODE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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