S71AL016D SPANSION [SPANSION], S71AL016D Datasheet - Page 73

• Manufacturer Part Number: S71AL016D
• Description: Stacked Multi-Chip Product (MCP) Flash Memory and RAM
• Manufacturer: SPANSION [SPANSION]

Notes:
1. The internal write time of the memory is defined by the overlap of WE#, CE# = V
2. Data I/O is high-impedance if OE# = V
3. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state.
4. During this period, the I/Os are in output state and input signals should not be applied.
Notes:
1. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state.
2. During this period, the I/Os are in output state and input signals should not be applied.
August 4, 2004 SRAM_Type04_04A0
BHE#/BLE#
BHE#/BLE#
ADDRESS
ADDRESS
DATA I/O
must be Active to initiate a write, and any of these signals can terminate a write by going Inactive. The data input set-up and
hold timing should be referenced to the edge of the signal that terminates the write.
DATAI/O
W E #
CE#
OE#
CE#
WE#
NOTE 2
NOTE 4
t
SA
Figure 7. Write Cycle 3 (WE# Controlled, OE# LOW)
t
HZOE
Figure 6. Write Cycle 2 (CE# Controlled)
t
HZWE
P r e l i m i n a r y
IH
.
t
SA
t
AW
2Mbit Type 2 SRAM
t
AW
t
t
BW
S C E
t
WC
t
WC
t
PWE
t
BW
DATA
t
t
PWE
SD
t
IN
SCE
DATA
t
SD
VALID
IN
VALID
IL
, BHE# and/or BLE# = V
t
HA
t
t
HA
LZWE
t
t
HD
H D
IL
. All signals
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