S71AL016D SPANSION [SPANSION], S71AL016D Datasheet
S71AL016D
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S71AL016D Summary of contents
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... S71AL016D based MCPs Stacked Multi-Chip Product (MCP) Flash Memory and RAM 16 Megabit ( 16-bit) CMOS 3.0 Volt-only Flash Memory and 2 Megabit (128K x 16-bit) Static RAM/ Pseudo Static RAM Distinctive Characteristics MCP Features Power supply voltage of 2.7 to 3.1 volt High performance — General Description ...
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... S71AL016D02-TF S71AL016D02-BF S71AL016D02-T7 S71AL016D02- SRAM density (p)SRAM Access time (ns SRAM SRAM SRAM SRAM S71AL016D based MCPs SRAM type Package 70 SRAM2 TLC056 70 SRAM2 TLC056 70 SRAM1 TLC056 70 SRAM1 TLC056 S71AL016D_02_04_00_A1 November 11, 2004 ...
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... Chip Erase Command Sequence ................................................................... 29 Sector Erase Command Sequence ................................................................ 30 Erase Suspend/Erase Resume Commands ....................................................31 Figure 4. Erase Operation.................................................... 32 Command Definitions ........................................................................................33 Table 9. S29AL016D Command Definitions ........................... 33 November 11, 2004 S71AL016D_02_04_00_A1 Write Operation Status . . . . . . . . . . . . . . . . . . . . 34 DQ7: Data# Polling ............................................................................................ 34 Figure 5. Data# Polling Algorithm ........................................ 35 RY/BY#: Ready/Busy# ....................................................................................... 35 DQ6: Toggle Bit I ............................................................................................... 36 DQ2: Toggle Bit II ...
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... Figure 7. Write Cycle 3 (WE# Controlled, OE# LOW) .............. 73 Figure 8. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low) ..... 74 Typical DC and AC Parameters . . . . . . . . . . . . . 74 Figure 9. Operating Current vs. Supply Voltage ..................... 74 Figure 10. Standby Current vs. Supply Voltage...................... 74 Figure 11. Access Time vs. Supply Voltage............................ 75 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 1. Truth Table ........................................................... 75 Revision Summary S71AL016D_02_04_00_A1 November 11, 2004 ...
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... MCP Block Diagram CE#f RST#f Shared Address OE# WE# CE1#s UB# LB# CE2s November 11, 2004 S71AL016D_02_04_00_A1 Flash CCS pSRAM/SRAM IO - CE1# UB# LB# CE2 RY/BY ...
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... DQ10 VCCf VCCs DQ12 DQ7 DQ2 DQ11 RFU DQ5 DQ14 Flash Only Address Legend B8 Flash only A15 C8 RAM only RFU D8 RFU Reserved for Future Use E8 A16 F8 RFU G8 VSS Shared Addresses S71AL016D_02_04_00_A1 November 11, 2004 ...
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... OE# WE# RY/BY# UB# LB# RST RFU Logic Symbol November 11, 2004 S71AL016D_02_04_00_A1 Address Inputs (Common Address Inputs (Flash Data Inputs/Outputs (Common) = Chip Enable 1 (Flash) = Chip Enable 1 (SRAM) = Chip Enable 2 (SRAM) = Output Enable (Common) = Write Enable (Common) ...
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... PACKAGE TYPE BA = Fine-pitch BGA Lead (Pb)-free compliant package BF = Fine-pitch BGA Lead (Pb)-free package SRAM DENSITY 02 = 2Mb SRAM PROCESS TECHNOLOGY D = 200 nm, Floating Gate Technology FLASH DENSITY 016 = 16Mb PRODUCT FAMILY S71AL Multi-chip Product (MCP) 3.0-volt Flash Memory and RAM ° C) S71AL016D_02_04_00_A1 November 11, 2004 ...
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... S71AL016D02 Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. November 11, 2004 S71AL016D_02_04_00_A1 Package Modifier/ Model Number Packing Type (Note 1) ...
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... WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS PIN A1 CORNER 3348 \ 16-038.22a S71AL016D_02_04_00_A1 November 11, 2004 ...
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S29AL016D 16 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory Datasheet Distinctive Characteristics Architectural Advantages Single power supply operation — Full voltage range: 2.7 to 3.6 volt read and write op- erations for ...
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General Description The S29AL016D Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball FBGA, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) ...
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The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset ...
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Product Selector Guide Family Part Number Speed Option Voltage Range: V Max access time ACC Max CE# access time Max OE# access time Note: See “AC Characteristics” for full ...
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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory ...
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WE# should remain at V pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after ...
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the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V ± ...
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Table 2. Sector Address Tables (Top Boot Device) Sector A19 A18 A17 A16 A15 A14 A13 A12 SA0 SA1 SA2 SA3 SA4 0 0 ...
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Table 3. Sector Address Tables (Bottom Boot Device) Sector A19 A18 A17 A16 A15 A14 A13 A12 SA0 SA1 SA2 SA3 ...
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Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” section. Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode ...
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possible to determine whether a sector is protected or unprotected. See “Au- toselect Mode” for details. Sector protection/unprotection can be implemented via two methods. The primary method requires V mented either ...
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START PLSCNT = 1 RESET Wait 4 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Wait 100 µs ...
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Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft- ware algorithms to be used for entire families of ...
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Addresses Addresses (Word Mode) (Byte Mode) 1Bh 36h 1Ch 38h 1Dh 3Ah 1Eh 3Ch 1Fh 3Eh 20h 40h 21h 42h 22h 44h 23h 46h 24h 48h 25h 4Ah 26h 4Ch Addresses Addresses (Word Mode) (Byte Mode) 27h 4Eh 28h 50h ...
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Table 8. Primary Vendor-Specific Extended Query Addresses Addresses (Word Mode) (Byte Mode) 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah ...
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Logical Inhibit Write cycles are inhibited by holding any one of OE initiate a write cycle, CE# and WE# must be a logical zero while OE logical one. Power-Up Write Inhibit If ...
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Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table sequences. Writing incorrect address and data values or writing them in the improper sequence resets ...
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Table 9 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires V on address bit A9. ID The autoselect command sequence is initiated by ...
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During the unlock bypass mode, only the Unlock Bypass Program and Unlock By- pass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset ...
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Any commands written to the chip during the Embedded Erase algorithm are ig- nored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reiniti- ated once the device ...
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Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase oper- ation and then read data from, or program data to, any sector not selected for erasure. ...
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Notes: 1. See Table 9 for erase command sequence. 2. See “DQ3: Sector Erase Timer” for more information START Write Erase ...
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Command Definitions Table 9. S29AL016D Command Definitions Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Top Boot Block Byte Word ...
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Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining ...
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Notes Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is ...
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If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend ...
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Figure 6 shows the toggle bit algorithm in flowchart form, and the section “Read- ing Toggle Bits DQ6/DQ2” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 20 differences between ...
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Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text. DQ5: Exceeded Timing Limits DQ5 indicates whether the ...
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The DQ5 failure condition may appear if the system tries to program a “1” location that is previously programmed to “0.” Only an erase operation can change a “0” back to ...
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Absolute Maximum Ratings Storage Temperature Plastic Packages .–65°C to ...
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Characteristics CMOS Compatible Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes ...
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DC Characteristics (continued) Zero Power Flash 500 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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Note °C August 4, 2004 S29AL016D_00_A1_E Frequency in MHz Figure ...
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Test Conditions Output Load Output Load Capacitance, C (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels ...
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Key to Switching Waveforms WAVEFORM Don’t Care, Any Change Permitted V CC 0.5 V Input CC 0.0 V Figure 12. Input Waveforms and Measurement Levels August 4, 2004 S29AL016D_00_A1_E ...
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AC Characteristics Read Operations Parameter JEDEC Std Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output ...
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Characteristics Hardware Reset (RESET#) Parameter JEDEC Std Description RESET# Pin Low (During Embedded Algorithms) t READY to Read or Write (See Note) RESET# Pin Low (NOT During Embedded t READY Algorithms) to ...
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AC Characteristics Word/Byte Configuration (BYTE#) Parameter JEDEC Std Description t t CE# to BYTE# Switching Low or High ELFL/ ELFH t BYTE# Switching Low to Output HIGH Z FLQZ t BYTE# Switching High to Output Active FHQV CE# OE# BYTE# ...
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CE# WE# BYTE# Note: Refer to the Erase/Program Operations table for t Figure 16. BYTE# Timings for Write Operations August 4, 2004 S29AL016D_00_A1_E ...
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AC Characteristics Erase/Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH ...
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Characteristics Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data, ...
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AC Characteristics Erase Command Sequence (last two cycles Addresses 2AAh CE Data RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid Address ...
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Characteristics t Addresses VA t ACC OE# t OEH WE# DQ7 DQ6–DQ0 t BUSY RY/BY# after command sequence, last status read cycle, and array data read ...
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AC Characteristics Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 21. ...
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Characteristics RESET# SA, A6, A1, A0 Sector Group Protect/Unprotect Data 60h 1 µs CE# WE# OE# Note: For sector protect ...
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AC Characteristics Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time DVEH ...
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Characteristics 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes program address program data, ...
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Erase and Programming Performance Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Byte Mode Chip Programming Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the following conditions: 25 data pattern. ...
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Type 1 SRAM Common Features Single Wide Power Supply Range 2.3 to 3.6 Volts Very low standby current 2.0µA at 3.0V (Typical) Very low operating current 2.0mA at 3.0V and 1µs (Typical) Very low Page Mode operating current 0.8mA ...
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Functional Description CE# CE2 WE# OE (Note Notes: 1. When UB# and LB# are in ...
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Operating Characteristics (Over Specified Temperature Range) Item Supply Voltage Data Retention Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Supply Current at 1 µs Cycle Time (Note ...
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Page Address (A4 - A16) Word Address (A0 - A3) CE1# CE2 OE# LB#, UB# Figure 1. Power Savings with Page Mode (WE Note: Page mode operation is a method of addressing the SRAM to save operating current. ...
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Timing Item Read Cycle Time Address Access Time Chip Enable to Valid Output Output Enable to Valid Output Byte Select to Valid Output Chip Enable to Low-Z output Output Enable to Low-Z Output Byte Select to Low-Z Output Chip Disable ...
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Timing Diagrams Address Data Out Previous Data Valid Figure 2. Timing of Read Cycle (CE Address CE1# CE2 OE# LB#, UB# High-Z Data Out Figure 3. Timing Waveform of Read Cycle (WE ...
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Address CE1# CE2 LB#, UB# WE# High-Z Data In Data Out Figure 4. Timing Waveform of Write Cycle (WE# Control) Address CE1# (for CE2 Control, use inverted signal) LB#, UB# WE# Data In Data Out Figure 5. Timing Waveform of ...
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Type 2 SRAM 128K x 16 Static RAM Common Features High Speed — 55ns and 70ns availability Ultra-low active power — Typical active current: 1 1MHz — Typical active current ...
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Operating Range Industrial Product Portfolio V Range (note (min) CC (typ.) CC (max) 2.7V 3.0V 3.3V Notes –2.0V for pulse durations less than 20 ns. IL(min.) 2. Typical values are included ...
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Capacitance Parameter C Input Capacitance IN C Output Capacitance OUT Note: Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms OUTPUT 30 pF INCLUDING JIG AND SCOPE ...
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V CC CE# or BHE#.BLE# Note: BHE#.BLE# is the AND of both BHE# and BLE#. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE# and BLE#. August 4, 2004 SRAM_Type04_04A0 ...
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Switching Characteristics Parameter Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE# Low to Data Valid ACE t OE# Low to Data Valid DOE t OE# Low ...
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Switching Waveforms ADDRESS DATA OUT PREVIOUS DATA VALID Figure 3. Read Cycle 1 (Address Transition Controlled) Notes: 1. Device is continuously selected. OE#, CE WE# is High for read cycle. ADDRESS CE# t ACE OE# BHE#/BLE# t ...
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ADDRESS CE BHE#/BLE# OE# DATA I/O NOTE 4 t HZOE Notes: 1. The internal write time of the memory is defined by the overlap of WE#, CE must be Active to initiate a ...
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ADDRESS CE BHE#/BLE# OE# DATA I/O NOTE 4 t HZOE Notes: 1. The internal write time of the memory is defined by the overlap of WE#, CE must be Active to initiate a write, and ...
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ADDRESS CE# BHE#/BLE WE# DATA I/O NOTE 2 Figure 8. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low) Notes CE# goes High simultaneously with WE# High, the output remains in a high-impedance state. 2. During this period, ...
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Truth Table CE# WE# OE# BHE# BLE ...
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... MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion LLC. Other company and product names used this publication are for identification purposes only and may be trademarks of their respective companies " at page 50,56. OES Revision Summary product under development by TM S71AL016D_02_04_00_A0 November 11, 2004 ...