S71AL016D SPANSION [SPANSION], S71AL016D Datasheet - Page 16

• Manufacturer Part Number: S71AL016D
• Description: Stacked Multi-Chip Product (MCP) Flash Memory and RAM
• Manufacturer: SPANSION [SPANSION]

16
Writing Commands/Command Sequences
Program and Erase Operation Status
Standby Mode
and gates array data to the output pins. WE# should remain at V
pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the com-
mand register contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read Operations
table for timing specifications and to
DC Characteristics table represents the active current specification for reading ar-
ray data.
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to V
For program operations, the BYTE# pin determines whether the device accepts
program data in bytes or words. Refer to “Word/Byte Configuration” for more
information.
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The “Word/Byte Program
Command Sequence” section has details on programming data to the device
using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Tables
address” consists of the address bits required to uniquely select a sector. The
“Command Definitions” section has details on erasing a sector or the entire chip,
or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the
autoselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7–DQ0. Standard read
cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
the write mode. The “AC Characteristics” section contains timing specification ta-
bles and timing diagrams for write operations.
During an erase or program operation, the system may check the status of the
operation by reading the status bits on DQ7–DQ0. Standard read cycle timings
and I
formation, and to “AC Characteristics” for timing diagrams.
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
CC2
in the DC Characteristics table represents the active current specification for
CC
2
read specifications apply. Refer to “Write Operation Status” for more in-
IL
and
, and OE# to V
3
indicate the address space that each sector occupies. A “sector
IH
.
A d v a n c e
S29AL016D
Figure 13
I n f o r m a t i o n
for the timing diagram. I
IH
. The BYTE#
CC1
S29AL016D_00_A1_E August 4, 2004
in the