AT52BR6408A ATMEL [ATMEL Corporation], AT52BR6408A Datasheet - Page 8
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AT52BR6408A
Manufacturer Part Number
AT52BR6408A
Description
64-Mbit Flash, 8-Mbit SRAM (x16 I/O)
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT52BR6408A.pdf
(37 pages)
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8
AT52BR6408A(T)
the protection register. After determining whether block B is protected or not or reading
the protection register, the Product ID Exit command must be given prior to performing
any other operation.
CFI: Common Flash Interface (CFI) is a published, standardized data structure that
may be read from a Flash device. CFI allows system software to query the installed
device to determine the configurations, various electrical and timing parameters, and
functions supported by the device. CFI is used to allow the system to learn how to inter-
face to the Flash device most optimally. The two primary benefits of using CFI are ease
of upgrading and second source availability. The command to enter the CFI Query
mode is a one-bus cycle command which requires writing data 98h to address 55h. The
CFI Query command can be written when the device is ready to read data or can also
be written when the part is in the product ID mode. Once in the CFI Query mode, the
system can read CFI data at the addresses given in Table 4 on page 25. To exit the CFI
Query mode, the product ID exit command must be given. If the CFI Query command is
given while the part is in the product ID mode, then the product ID exit command must
first be given to return the part to the product ID mode. Once in the product ID mode, it
will be necessary to give another product ID exit command to return the part to the read
mode.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro-
grams to the 64-Mbit device in the following ways: (a) V
(typical), the program function is inhibited. (b) V
reached the V
before programming. (c) Program inhibit: holding any one of OE low, CE high or WE
high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle. (e) V
INPUT LEVELS: While operating with a 2.7V to 3.1V power supply, the address inputs
and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely
affecting the operation of the device. The I/O lines can be driven from 0 to V
CC
sense level, the device will automatically time-out 10 ms (typical)
CC
PP
power-on delay: once V
CC
is less than V
sense: if V
ILPP
CC
is below 1.8V
.
3425A–STKD–1/04
CCQ
+ 0.6V.
CC
has