AT52BR6408A ATMEL [ATMEL Corporation], AT52BR6408A Datasheet - Page 7

• Manufacturer Part Number: AT52BR6408A
• Description: 64-Mbit Flash, 8-Mbit SRAM (x16 I/O)
• Manufacturer: ATMEL [ATMEL Corporation]

AT52BR6408A(T)
“0” while the erase or program operation is still in progress. Please see Table 3 on page
11 for more details.
V
STATUS BIT: The 64-Mbit device provides a status bit on I/O3 that provides infor-
PP
mation regarding the voltage level of the VPP pin. During a program or erase operation,
if the voltage on the VPP pin is not high enough to perform the desired operation suc-
cessfully, the I/O3 status bit will be a “1”. Once the V
status bit has been set to a “1”,
PP
the system must write the Product ID Exit command to return to the read mode. On the
other hand, if the voltage level is high enough to perform a program or erase operation
successfully, the V
status bit will output a “0”. Please see Table 3 on page 11 for more
PP
details.
ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the sys-
tem to interrupt a sector erase operation and then program or read data from a different
sector within the same plane. Since this device has a multiple plane architecture, there
is no need to use the erase suspend feature while erasing a sector when you want to
read data from a sector in another plane. After the Erase Suspend command is given,
the device requires a maximum time of 15 µs to suspend the erase operation. After the
erase operation has been suspended, the plane that contains the suspended sector
enters the erase-suspend-read mode. The system can then read data or program data
to any other sector within the device. An address is not required during the Erase Sus-
pend command. During a sector erase suspend, another sector cannot be erased. To
resume the sector erase operation, the system must write the Erase Resume command.
The Erase Resume command is a one-bus cycle command, which does require the
plane address. The device also supports an erase suspend during a complete chip
erase. While the chip erase is suspended, the user can read from any sector within the
memory that is protected. The command sequence for a chip erase suspend and a sec-
tor erase suspend are the same.
PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows
the system to interrupt a programming operation and then read data from a different
word within the memory. After the Program Suspend command is given, the device
requires a maximum of 10 µs to suspend the programming operation. After the program-
ming operation has been suspended, the system can then read from any other word
within the device. An address is not required during the program suspend operation. To
resume the programming operation, the system must write the Program Resume com-
mand. The program suspend and resume are one-bus cycle commands. The command
sequence for the erase suspend and program suspend are the same, and the command
sequence for the erase resume and program resume are the same.
128-BIT PROTECTION REGISTER: The 64-Mbit device contains a 128-bit register that
can be used for security purposes in system design. The protection register is divided
into two 64-bit blocks. The two blocks are designated as block A and block B. The data
in block A is non-changeable and is programmed at the factory with a unique number.
The data in block B is programmed by the user and can be locked out such that data in
the block cannot be reprogrammed. To program block B in the protection register, the
four-bus cycle Program Protection Register command must be used as shown in the
Command Definition in Hex table on page 12. To lock out block B, the four-bus cycle
lock protection register command must be used as shown in the Command Definition in
Hex table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during
the fourth bus cycle are don’t cares. To determine whether block B is locked out, the
Product ID Entry command is given followed by a read operation from address 80H. If
data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be repro-
grammed. Please see the Protection Register Addressing Table on page 13 for the
address locations in the protection register. To read the protection register, the Product
ID Entry command is given followed by a normal read operation from an address within
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