AT52BR6408A ATMEL [ATMEL Corporation], AT52BR6408A Datasheet - Page 32

• Manufacturer Part Number: AT52BR6408A
• Description: 64-Mbit Flash, 8-Mbit SRAM (x16 I/O)
• Manufacturer: ATMEL [ATMEL Corporation]

Timing Diagrams
Read Cycle 1
Read Cycle 2
Read Cycle 3
Notes:
32
1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
2. SOE = V
3. Transition is measured ± 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
AT52BR6408A(T)
DATA OUT
status.
standby, low for active.
DATA OUT
ADDRESS
SUB, SLB
DATA OUT
ADDRESS
SUB, SLB
SCS1
SCS2
(1),(4)
(1),(2),(4)
(1),(2),(4)
SCS1
SCS2
SOE
IL
.
HIGH-Z
PREVIOUS DATA
t
CLZ
(3)
t
OH
t
BLZ
t
t
t
t
t
AA
ACS
OLZ
CLZ
AA
(3)
(3)
(3)
t
BA
t
ACS
t
OE
t
RC
t
RC
DATA VALID
DATA VALID
DATA VALID
t
OHZ
t
BHZ
(3)
t
(3)
CHZ
t
t
OH
CHZ
t
OH
(3)
(3)
3425A–STKD–1/04