AT52BR6408A ATMEL [ATMEL Corporation], AT52BR6408A Datasheet - Page 6

• Manufacturer Part Number: AT52BR6408A
• Description: 64-Mbit Flash, 8-Mbit SRAM (x16 I/O)
• Manufacturer: ATMEL [ATMEL Corporation]

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AT52BR6408A(T)
PROGRAM/ERASE STATUS: The device provides several bits to determine the status
of a program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7. All other status bits are
don’t care. Table 3 on page 11 and the following four sections describe the function of
these bits. To provide greater flexibility for system designers, the 64-Mbit device con-
tains a programmable configuration register. The configuration register allows the user
to specify the status bit operation. The configuration register can be set to one of two dif-
ferent values, “00” or “01”. If the configuration register is set to “00”, the part will
automatically return to the read mode after a successful program or erase operation. If
the configuration register is set to a “01”, a Product ID Exit command must be given after
a successful program or erase operation before the part will return to the read mode. It
is important to note that whether the configuration register is set to a “00” or to a “01”,
any unsuccessful program or erase operation requires using the Product ID Exit com-
mand to return the device to read mode. The default value (after power-up) for the
configuration register is “00”. Using the four-bus cycle set configuration register com-
mand as shown in the Command Definition table on page 12, the value of the
configuration register can be changed. Voltages applied to the reset pin will not alter the
value of the configuration register. The value of the configuration register will affect the
operation of the I/O7 status bit as described below.
DATA POLLING: The 64-Mbit device features Data Polling to indicate the end of a pro-
gram cycle. If the status configuration register is set to a “00”, during a program cycle an
attempted read of the last word loaded will result in the complement of the loaded data
on I/O7. Once the program cycle has been completed, true data is valid on all outputs
and the next cycle may begin. During a chip or sector erase operation, an attempt to
read the device will give a “0” on I/O7. Once the program or erase cycle has completed,
true data will be read from the device. Data Polling may begin at any time during the pro-
gram cycle. Please see Table 3 on page 11 for more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while
the device is actively programming or erasing data. I/O7 will go high when the device
has completed a program or erase operation. Once I/O7 has gone high, status informa-
tion on the other pins can be checked.
The Data Polling status bit must be used in conjunction with the erase/program and V
status bit as shown in the algorithm in Figures 2 and 3.
TOGGLE BIT: In addition to Data Polling, the 64-Mbit device provides another method
for determining the end of a program or erase cycle. During a program or erase opera-
tion, successive attempts to read data from the memory will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling
and valid data will be read. Examining the toggle bit may begin at any time during a pro-
gram cycle. Please see Table 3 on page 11 for more details.
The toggle bit status bit should be used in conjunction with the erase/program and V
status bit as shown in the algorithm in Figures 4 and 5 on page 10.
ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5 that indicates
whether the program or erase operation has exceeded a specified internal pulse count
limit. If the status bit is a “1”, the device is unable to verify that an erase or a word pro-
gram operation has been successfully performed. The device may also output a “1” on
I/O5 if the system tries to program a “1” to a location that was previously programmed to
a “0”. Only an erase operation can change a “0” back to a “1”. If a program (Sector
Erase) command is issued to a protected sector, the protected sector will not be pro-
grammed (erased). The device will go to a status read mode and the I/O5 status bit will
be set high, indicating the program (erase) operation did not complete as requested.
Once the erase/program status bit has been set to a “1”, the system must write the
Product ID Exit command to return to the read mode. The erase/program status bit is a
3425A–STKD–1/04
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