9UMS9001AKLF IDT [Integrated Device Technology], 9UMS9001AKLF Datasheet - Page 9

• Manufacturer Part Number: 9UMS9001AKLF
• Description: PC MAIN CLOCK - CK540
• Manufacturer: IDT [Integrated Device Technology]

IDT
1
2
3
4
5
CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets
CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate
calculations
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7
8
9
Notes on Electrical Characteristics:
Electrical Characteristics - REF-14.318MHz
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through Vswing centered around differential zero
Vxabs is defined as the voltage where CLK = CLK#
Only applies to the differential rising edge (CLK rising and CLK# falling)
Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
Operation under these conditions is neither implied, nor guaranteed.
Maximum input voltage is not to exceed maximum VDD
See PCI Clock-to-Clock Delay Figure
9UMS9001
PC MAIN CLOCK - CK540
®
Absolute min/max period
Falling Edge Slew Rate
PC MAIN CLOCK - CK540
Rising Edge Slew Rate
Output High Voltage
Output High Current
Output Low Voltage
Output Low Current
Long Accuracy
PARAMETER
Clock period
Duty Cycle
Jitter
SYMBOL
t
T
jcyc-cyc
ppm
T
V
V
t
t
period
I
I
d
SLR
FLR
OH
OL
abs
OH
OL
t1
see Tperiod min-max values
Measured from 0.8 to 2.0 V
Measured from 2.0 to 0.8 V
14.318MHz output nominal
14.318MHz output nominal
V
V
V
V
OH
OL
OH
OL
CONDITIONS
@MAX = 3.135 V
@MIN = 1.95 V,
I
@MAX = 0.4 V
@MIN = 1.0 V,
I
OH
V
V
OL
T
T
= -1 mA
= 1 mA
= 1.5 V
= 1.5 V
9
69.8203
69.8203
-300
MIN
2.4
-33
30
45
1
1
70.86224
69.8622
1000
MAX
300
-33
0.4
38
55
4
4
Advance Information
UNITS Notes
V/ns
V/ns
ppm
mA
mA
ns
ns
ps
%
V
V
1,2
2
2
1
1
1
1
1
1
1
1
1247B—07/19/10