S71WS512NB0BAEZZ0 SPANSION [SPANSION], S71WS512NB0BAEZZ0 Datasheet - Page 21

• Manufacturer Part Number: S71WS512NB0BAEZZ0
• Description: Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
• Manufacturer: SPANSION [SPANSION]

Input/Output Descriptions
June 28, 2004 S71WS512NE0BFWZZ_00_A1
A23-A0
DQ15-DQ0
CE#
OE#
WE#
V
V
V
V
NC
RDY
CLK
AVD#
RESET#
WP#
ACC
CC
IO
SS
SSIO
A d v a n c e
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
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I n f o r m a t i o n
Address inputs for WS256N
Data input/output
Chip Enable input. Asynchronous relative to CLK for
the Burst mode.
Output Enable input. Asynchronous relative to CLK
for the Burst mode.
Write Enable input.
Device Power Supply
(1.65 – 1.95 V).
Input & Output Buffer Power Supply (1.35 – 1.70 V).
Ground
Output Buffer Ground
No Connect; not connected internally
Ready output. Indicates the status of the Burst read.
Clock input. In burst mode, after the initial word is
output, subsequent active edges of CLK increment
the internal address counter. Should be at V
while in asynchronous mode
Address Valid input. Indicates to device that the
valid address is present on the address inputs.
Low = for asynchronous mode, indicates valid
address; for burst mode, causes starting address to
be latched.
High = device ignores address inputs
Hardware reset input. Low = device resets and
returns to reading array data
Hardware write protect input. At V
program and erase functions in the four outermost
sectors. Should be at V
Accelerated input. At V
programming; automatically places device in unlock
bypass mode. At V
functions. Should be at V
IL
, disables all program and erase
HH
IH
IH
, accelerates
for all other conditions.
for all other conditions.
IL
, disables
IL
or V
IH
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