S71WS512NB0BAEZZ0 SPANSION [SPANSION], S71WS512NB0BAEZZ0 Datasheet - Page 140

• Manufacturer Part Number: S71WS512NB0BAEZZ0
• Description: Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
• Manufacturer: SPANSION [SPANSION]

TIMING DIAGRAMS (Continued)
Notes
140
Configuration Register Set Timing #1 (Asynchronous Operation)
ADDRESS
CE#1
OE#
WE#
LB#, UB#
DQ*
*1: The all address inputs must be High from Cycle #1 to #5.
*2: The address key must confirm the format specified in FUNCTIONAL DESCRIPTION. If not, the operation
*3: After t
3
and data are not guaranteed.
operation. t
spectively.
CP
Cycle #1
MSB*
or t
t
RC
CP
RC
RDa
1
and t
following Cycle #6, the Configuration Register Set is completed and returned to the normal
t
CP
RC
Cycle #2
MSB*
are applicable to returning to asynchronous mode and to synchronous mode re-
t
WC
RDa
1
t
CP
Cycle #3
MSB*
t
128Mb pSRAM
WC
RDa
P r e l i m i n a r y
1
t
CP
Cycle #4
MSB*
t
WC
X
1
t
CP
Cycle #5
MSB*
t
WC
X
1
S71WS512NE0BFWZZ_00_A1 June 28, 2004
t
CP
Cycle #6
Key*
t
RC
RDb
2
(t
t
CP
RC
*
)
3