ZL50070GAC ZARLINK [Zarlink Semiconductor Inc], ZL50070GAC Datasheet - Page 32

• Manufacturer Part Number: ZL50070GAC
• Description: 24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 96 Inputs and 96 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

•
The TAP signals are only applied when the ZL50070 is required to be in test mode. When in normal, non-test mode,
TRST must be connected low to disable the test logic. The remaining test pins may be left unconnected.
12.2
The ZL50070 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG interface contains a
16-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP
controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to
select the test data register that may operate while the instruction is current and to define the serial test data
register path that is used to shift data between TDi and TDo during register scanning.
12.3
As specified in the IEEE 1149.1 standard, the ZL50070 JTAG Interface contains three test data registers:
•
•
•
12.4
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE-1149.1 test interface.
13.0
The memory map for the ZL50070 is given in Table 12.
Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to V
driven from an external source. When JTAG is not in use, this pin must be tied low for normal operation.
The Boundary-Scan Register - The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the ZL50070 core logic.
The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from
TDi to TDo.
The Device Identification Register - The JTAG device ID for the ZL50070 is C39614B
Address (Hex)
28000 - 2DFFF
2E000 - 2FFFF
18000 - 1FFFF
00000 - 17FFF
20000 - 25FFF
26000 - 27FFF
30000 - 35FFF
Instruction Register
Test Data Register
Boundary Scan Description Language (BSDL)
Memory Map of ZL50070
Version
Part Number
Manufacturer ID
LSB
Connection Memory
Invalid Address. Access causes Bus error (BERR)
Connection Memory LSB
Invalid Address. Access causes Bus error (BERR)
Data Memory: Read only; Bus error on write (BERR)
Invalid Address. Access causes Bus error (BERR)
Input BER Enable Control Memory.
<31:28>
<27:12>
<11:1>
<0>
Table 12 - Memory Map
Zarlink Semiconductor Inc.
ZL50070
32
Description
0000
1100 0011 1001 0110
0001 0100 101
1
DD_IO
H
when it is not
Data Sheet