ZL50070GAC ZARLINK [Zarlink Semiconductor Inc], ZL50070GAC Datasheet - Page 11

• Manufacturer Part Number: ZL50070GAC
• Description: 24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 96 Inputs and 96 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
D4, F4, G3, G2, G1, L2, N3,
AA7, W10, Y11, Y12, AB17,
T1, U2, T6, V5, AA3, W7,
AA18, W18, V19, AA22,
U21, N17
K3, K19
J2, G21
AA13
W12
Pin
SToD0-23
CKi1-2
FPi1-2
Name
CKi0
FPi0
Zarlink Semiconductor Inc.
Serial TDM Output Data ’D’ Streams (5 V Tolerant, 3.3 V
Tri-state Slew-Rate Controlled Outputs)
The data rate of these output streams can be selected in a group of
4 to be either 8.192 Mbps or 16.384 Mbps. The stream is unused
when its output group rate is 65.536 Mbps or 32.678 Mbps. Refer to
Section 1.5 for rate programming options.
The data streams can be selected to be either inverted or
non-inverted, programmed by the Group Control Registers (Section
14.4).
Unused outputs are tristated and may be left unconnected.
ST-BUS/GCI-Bus Clock Input (5 V Tolerant Schmitt-Triggered
Input)
This pin accepts an 8.192 MHz, 16.384 MHz, 32.678 MHz or
65.536 MHz clock. This clock must be provided for correct
operation of the
selected by the CK_SEL1-0 inputs. The active clock edge may be
either rising or falling, programmed by the Input Clock Control
Register (Section 14.5).
ST-BUS/GCI-Bus Frame Pulse Input (5 V Tolerant Input)
This pin accepts the 8 kHz frame pulse which marks the frame
boundary of the TDM data streams. The pulse width is nominally
one CKi0 clock period (assuming ST-BUS mode) selected by the
CK_SEL1-0 inputs. The active state of the frame pulse may be
either high or low, programmed by the Input Clock Control Register
(Section 14.5).
ST-BUS/GCI-Bus Clock Inputs (5 V Tolerant Schmitt Triggered
Inputs)
These optional TDM clock inputs are at 8.192 MHz, 16.384 MHz,
32.678 MHz or 65.536 MHz. The frequency of each clock input is
automatically detected by the ZL50070. Refer to Section 2.0 for
TDM timing options. The active clock edge may be either rising or
falling, programmed by the Input Clock Control Register (Section
14.5). Unused inputs must be connected to a defined logic level.
ST-BUS/GCI-Bus Frame Pulse Inputs (5 V Tolerant Inputs)
These 8 kHz input pulses correspond to the optional CKi2-1 clock
inputs. The frame pulses mark the frame boundary of the TDM data
streams. Refer to Section 2.0 for TDM timing options. Each pulse
width is nominally one CKi clock period (assuming ST-BUS mode).
The active state of the frame pulse may be either high or low,
programmed by the Input Clock Control Register (Section 14.5).
Unused inputs must be connected to a defined logic level.
ZL50070
11
ZL50070.
The frequency of the CKi0 input is
Description
Data Sheet