ZL50070GAC ZARLINK [Zarlink Semiconductor Inc], ZL50070GAC Datasheet - Page 28

• Manufacturer Part Number: ZL50070GAC
• Description: 24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 96 Inputs and 96 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

† Don’t Care. A0 is not used
10.4
10.4.1
The operation of a read cycle is illustrated in Figure 10.
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40200 or
40201
40282 or
40283
40286 or
40287
40284 or
40285
Address
The microprocessor asserts the R/W control signal high, to signal a read cycle. It also drives the address A,
transfer size, SIZ1 - 0, and chip select logic drives the CS signal active low to select the ZL50070
The microprocessor then drives the DS signal active low, to signal the start of the bus cycle. The DS signal
is held low for the duration of the bus cycle
WAIT is asserted active low
The ZL50070 accesses the requested memory or register location(s), and places the requested data onto
the data bus, D31 - 0 (D15 - 0 in 16 bit Mode). All data bus pins are driven, whether or not they are being
used for the specific data transfer. Unused pins will present unknown data. If the address is to an unused
area of the memory space, unknown data is presented on the data bus
The ZL50070 then de-asserts WAIT, and asserts either DTA or BERR, depending on the validity of the data
transfer
When the microprocessor observes the active low state of the DTA or the BERR signal, or the low-to-high
transition of the WAIT signal, it terminates the bus cycle by driving the DS pin inactive high
When the ZL50070 sees the DS signal go inactive high, it removes the assertions on the DTA or BERR
signals by driving them inactive high
When the ZL50070 sees the CS signal go inactive high, it tri-states the data bus, D31 - 0 (D15 - 0 in 16 bit
Mode) and the DTA, BERR and the WAIT signals. However, if CS goes inactive high before DS goes inactive
high, the DTA, BERR and WAIT signals are driven inactive high before they are tri-stated
At the end of an Intel bus cycle, DTA is always driven low to indicate the end of the data transfer, regardless
of BERR
(Hex)
Bus Operation
Read Cycle
Group Control
Register (Group 0)
Input Clock Control
Register
Output Clock
Control Register
Output Clock
Control Register
Description
Register
Table 11 - 16 Bit Mode Example Byte Address
Bits 23:16
Bits 15:8
Bits 15:0
Bits 31:16
Register
Byte
Zarlink Semiconductor Inc.
100 0000 0010 0000 000X
100 0000 0010 1000 001X
100 0000 0010 1000 011X
100 0000 0010 1000 010X
ZL50070
28
A18 - 0 (binary)
†
†
†
†
SIZ1
1
0
0
0
SIZ0
0
1
0
0
16 bit transfer
16 bit transfer
8 bit transfer
8 bit transfer
Comments
Data Sheet