ZL50070GAC ZARLINK [Zarlink Semiconductor Inc], ZL50070GAC Datasheet - Page 18

• Manufacturer Part Number: ZL50070GAC
• Description: 24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 96 Inputs and 96 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

1.5
The ZL50070 supports rate conversion from any input stream rate to any output stream rate.
An example of ZL50070 rate conversion is given in Figure . Here the total capacity of both the input and the output
is 24,576 channels. The output stream rates do not have to follow the input stream rates. In this example, on the
input side of the switch you have 16 streams operating at 65.536 Mbps (16,384 channels - 16 groups with 1 stream
in each group), 8 streams operating at 32.768 Mbps (4096 channels - 4 groups with 2 streams in each group) and
16 streams operating at 16.384 Mbps (4096 channels - 4 groups with 4 streams in each group) with no streams
operating at 8.192 Mbps. This results in a maximum input capacity of 24,576 input channels. As the output streams
do not have to follow the input streams, they can be configured so that 8 streams operate at 65.536 Mbps (8192
channels - 8 groups with 1 stream in each group), 24 streams operate at 32.768 Mbps (12,288 channels - 12
groups with 2 streams in each group), 16 streams operate at 16.384 Mbps (4096 channels - 4 groups with 4
streams in each group) and no streams at 8.192 Mbps. This results in a maximum output capacity of 24,576 output
channels. The reason that no stream is operating at 8.192 Mbps is that as soon as one group is set to this data rate,
the capacity of the device will be less than the full 24,576 channels.
2.0
The input timing for the ZL50070 can be set for one of four different frequencies. They can also be set for ST-BUS
or GCI-Bus mode with positive or negative input. The CKi0 and FPi0 input timing must be provided in order for the
device to be used. There are two additional input clocks and frame pulses that can be provided. CKi0 is used to
generate the internal clock. This clock is used for all the internal logic and can be used as one of the clocks that
defines the timing for the input and output data. The input stream clock source is selected by the ISSRC1 - 0 (bits 1
- 0) in the Group Control Register. The output stream clock source is selected by the OSSRC1 - 0 (bits 17 - 16) in
the Group Control Register.
The CKi0 and FPi0 input frequency is set via the CK_SEL1 - 0 pins as shown in Table 3. By default the CKi0 and
FPi0 pins accept ST-BUS, negative input timing. The input frame pulse format (ST-BUS/GCI-Bus), frame pulse
polarity, and clock polarity can be programmed by the GCISEL0 (bit 2), FPIPOL0 (bit 1), and CKIPSL0 (bit 0) in the
Input Clock Control Register (ICCR), as described in Section 14.5.
Example:
Input Groups 0 - 15 at 65 Mbps; Output Groups 0 - 7 at 65 Mbps
Input Groups 16 - 19 at 32 Mbps; Output Groups 8 - 19 at 32 Mbps
Input Groups 20 - 23 at 16 Mbps; Output Groups 20 - 23 at 16 Mbps
Rate Conversion
Input Clock (CKi) and Input Frame Pulse (FPi) Timing
20 - 23 at 16 Mbps
16 - 19 at 32 Mbps
0 - 15 at 65 Mbps
Input Groups
Input Groups
Input Groups
Figure 4 - Input and Output Data Rate Conversion Example
STiB16 - 19 at 32 Mbps
STiA16 - 19 at 32 Mbps
STiC20 - 23 at 16 Mbps
STiD20 - 23 at 16 Mbps
STiA20 - 23 at 16 Mbps
STiB20 - 23 at 16 Mbps
STiA0 - 15 at 65 Mbps
STiC16 - 19 Not Active
STiD16 - 19 Not Active
STiC0 - 15 Not Active
STiB0 - 15 Not Active
STiD0 - 15 Not Active
Zarlink Semiconductor Inc.
ZL50070
24 K x 24 K
18
SToC20 - 23 at 16 Mbps
SToD20 - 23 at 16 Mbps
SToA20 - 23 at 16 Mbps
SToB20 - 23 at 16 Mbps
SToA8 - 19 at 32 Mbps
SToB8 - 19 at 32 Mbps
SToA0 - 7 at 65 Mbps
SToC8 - 19 Not Active
SToD8 - 19 Not Active
SToC0 - 7 Not Active
SToB0 - 7 Not Active
SToD0 - 7 Not Active
Output Groups
8 - 19 at 32 Mbps
20 - 23 at 16 Mbps
Output Groups
Output Groups
0 - 7 at 65 Mbps
Data Sheet