ZL50057 ZARLINK [Zarlink Semiconductor Inc], ZL50057 Datasheet - Page 64

• Manufacturer Part Number: ZL50057
• Description: 12 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 48 Inputs and 48 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

14.0
This section describes the registers that are used in the device.
14.1
Address 0000
The Control Register defines which memory is to be accessed. It initiates the memory block programming mode
and selects the Backplane and Local data rate modes. The Control Register (CR) is configured as follows:
15:13
010D
012D
Bit
12
10
11
9
A14-A0
014D
3FFF
H
H
Control Register (CR)
MODE[2:0]
Detailed Register Descriptions
MODE32L
Reserved
- 014C
- 012C
FBDEN
SMPL_
MODE
Name
FBD_
H
H
H
.
H
H
Backplane Input Bit Rate Register 0 - 31, BIBRR0 - 31
Backplane Output Bit Rate Register 0 - 31, BOBRR0 - 31
Memory BIST Register, MBISTR
Device Identification Register, DIR
Reset
Value
0
0
0
0
0
Table 20 - Address Map for Registers (A14 = 0) (continued)
Frame Boundary Discriminator Mode
When set to 111
frequency and high frequency jitter.
When set to 000
frequency jitter only.
All other values are reserved.
These bits are ignored when FBDEN bit is LOW.
Sample Point Mode
When LOW the input bit sampling point is always at the 3/4 bit location. The input bit
fractional delay is programmed in 1/4 bit increments from 0 to 7 3/4 as per the value
of the LIDR0 to LIDR15 and BIDR0 to BIDR31 registers.
When HIGH, the input bit sampling point is programmed to the 3/4, 4/4, 1/4, 2/4 bit
location as per the value of the LIDR0 to LIDR15 and BIDR0 to BIDR31 registers. In
addition the incoming data can be delayed by 0 to 7 bits in 1 bit increments.
See Table 26, Table 27, Table 30 and Table 31 for details.
Reserved
Must be set to 0 for normal operation
Frame Boundary Discriminator Enable
When LOW, the frame boundary discriminator function is disabled.
When HIGH, enables frame boundary discriminator function which allows the
device to tolerate inconsistent frame boundaries, hence improving the tolerance to
cycle-to-cycle variation on the input clock.
Local 32MHz Mode
When LOW, Local streams LSTi0-15 and LSTo0-15 can be individually programmed
for data rates of 2, 4, 8, or 16 Mbps.
When HIGH, Local streams LSTi0-7 and LSTo0-7 operate at 32.768Mbps only and
LSTi8-15 and LSTo8-15 are unused.
Table 21 - Control Register Bits
B
B
Zarlink Semiconductor Inc.
, the Frame Boundary Discriminator can handle both low
, the Frame Boundary Discriminator is set to handle lower
ZL50057/8
64
Register
Description
Data Sheet