ZL50057 ZARLINK [Zarlink Semiconductor Inc], ZL50057 Datasheet - Page 63

• Manufacturer Part Number: ZL50057
• Description: 12 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 48 Inputs and 48 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.0
When the most significant bit, A14, of the address bus is set to ’0’, the microprocessor is performing an access to
one of the device’s internal registers. Address bits A13-A0 indicate which particular register is being accessed.
00CD
00ED
8:0
00A3
Bit
0003
0023
0043
0063
0083
A14-A0
00CC
00C3
00C4
00C5
00C6
00C7
00C8
00C9
00CA
00CB
0000
0001
0002
H
H
H
H
H
H
H
H
Internal Register Mappings
BCAB[8:0]
- 0012
- 0032
- 0062
- 0082
- 0092
- 00C2
- 00DC
- 00FC
Name
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Control Register, CR
Block Programming Register, BPR
BER Control Register, BERCR
Local Input Channel Delay Register 0 - 15, LCDR0 - 15
Local Input Bit Delay Register 0 - 15, LIDR0 - 15
Backplane Input Channel Delay Register 0 - 31, BCDR0 - 31
Backplane Input Bit Delay Register 0 - 31, BIDR0 - 31
Local Output Advancement Register 0 - 15, LOAR0 - 15
Backplane Output Advancement Register 0 - 31, BOAR0 - 31
Local BER Start Send Register, LBSSR
Local Transmit BER Length Register, LTXBLR
Local Receive BER Length Register, LRXBLR
Local BER Start Receive Register, LBSRR
Local BER Count Register, LBCR
Backplane BER Start Send Register, BBSSR
Backplane Transmit BER Length Register, BTXBLR
Backplane Receive BER Length Register, BRXBLR
Backplane BER Start Receive Register, BBSRR
Backplane BER Count Register, BBCR
Local Input Bit Rate Register 0 - 15, LIBRR0 - 15
Local Output Bit Rate Register 0 - 15, LOBRR0 - 15
Table 19 - BCM Bits for 32 Mbps Source-to-Backplane Switching
Source Channel Address Bits / Message Mode Data
The binary value of these 9 bits represents the input channel number, when BMM is LOW.
Bits BCAB[7:0] transmitted as data when BMM is set HIGH.
Note: When BMM is set HIGH, in both ST-BUS and GCI-Bus modes, the BCAB[7:0] bits
are output sequentially to the timeslot with BCAB[7] being output first.
Table 20 - Address Map for Registers (A14 = 0)
Zarlink Semiconductor Inc.
ZL50057/8
63
Description
Register
Data Sheet