ZL50057 ZARLINK [Zarlink Semiconductor Inc], ZL50057 Datasheet - Page 17

• Manufacturer Part Number: ZL50057
• Description: 12 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 48 Inputs and 48 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
LSTo8-15
LCSTo0-1
Microprocessor Port Signals
A0 - A14
Pin Name
C20, D18,
D19, D20,
E17, E18,
E19, E20
C17, C16
D5, C6, A6,
D7, C7, B7,
C8, B8, A8,
D9, B9, A9,
D10, C10,
A10
Coordinates
Package
(272-ball
ZL50057
PBGA)
D13, D14,
D15, D16,
E13, E14,
E15, E16
A16, A15
A1, A2, A3,
A4, A5, B5,
B6, B7, B8,
B9, C5, C6,
C7, C8, C9
Coordinates
Package
(256-ball
ZL50058
PBGA)
Zarlink Semiconductor Inc.
ZL50057/8
Local Serial Output Streams 8 to 15 (5 V Tolerant
Three-state Outputs with Slew-Rate Control).
In Local Non-32 Mbps Mode, these pins output serial TDM
data streams at a data rate of:
16.384 Mbps (with 256 channels per stream),
8.192 Mbps (with 128 channels per stream),
4.096 Mbps (with 64 channels per stream) or
2.048 Mbps (with 32 channels per stream).
The data rate is independently programmable for each output
stream.
These pins are unused when the Local 32 Mbps Mode is
selected. Therefore, the value output on these pins during
Local 32 Mbps Mode (either driven-HIGH or high impedance)
is dependent on the configuration of the LORS pin.
Refer to the descriptions of the LORS and ODE pins for
control of the output HIGH or high impedance state.
Local Output Channel High Impedance Control (5 V
Tolerant Three-state Outputs). These pins control external
buffering individually for a set of Local output streams on a
per-channel basis.
When LOW, the external output buffer will be tri-stated.
When HIGH, the external output buffer will be enabled.
In Local Non-32 Mbps Mode (stream rate 2 Mbps to 16 Mbps):
LCSTo0 is the output enable for LSTo0,2,4,6,8,10,12,14
LCSTo1 is the output enable for LSTo1,3,5,7,9,11,13,15
In Local 32Mbps Mode (stream rate 32 Mbps):
LCSTo0 is the output enable for LSTo0,2,4,6
LCSTo1 is the output enable for LSTo1,3,5,7
Refer to descriptions of the LORS and ODE pins for control of
the output LOW or active state.
Address 0 - 14 (5V Tolerant Inputs). These pins form the
15-bit address bus to the internal memories and registers.
A0 = LSB
17
Description
Data Sheet