AM79C850KCW AMD [Advanced Micro Devices], AM79C850KCW Datasheet - Page 66

• Manufacturer Part Number: AM79C850KCW
• Description: SUPERNET-R 3
• Manufacturer: AMD [Advanced Micro Devices]

PDX FUNCTIONAL DISCRIPTION
Introduction
The PDX is a digital CMOS core that is used in
SUPERNET 3. It employs new circuit techniques to
achieve clock and data recovery.
Traditionally, Phase-Locked-Loops (PLL) are used for
the purpose of clock recovery in data communication
areas. There are both analog and digital versions of the
PLL components such as phase detector, filter, charge
pump. A traditional PLL always contains a voltage-con-
trolled oscillator (VCO) to regenerate a clock which is
frequency synchronized to and phase aligned with the
received data.
The PDX employs techniques that are significantly
different from the traditional PLL. Not only are the
control functions completely digital, the VCO function is
also replaced by a proprietary delay-line technique. The
result is a highly integratable core which can be
manufactured in a standard digital CMOS process.
The PDX transmitter serializes encoded NRZ symbols.
The clock multiplier circuit generates a bit rate
(125 MHz) clock from the LSCLK reference. The serial
data stream is converted into NRZI for output to the
PMD transceiver.
The PDX receiver uses the clock recovery circuit to
extract clock information from the received data. The
recovered clock is used to operate the serial-to-parallel
conversion logic.
PDX FUNCTIONAL DESCRIPTION
The PDX accepts 4B5B encoded data symbols scram-
ble or non-scrambled from the PLC-S core at TDAT 4–0
inputs. The 5-bit symbol is clocked into the PDX by the
rising edge of LSCLK, serialized, converted to NRZI
format and shifted to the outputs. The TX+/TX– pair
carries PECL-compatible differential NRZI data to
the fiber optic transmitter or to the twisted-pair
transceiver interface.
The PDX uses LSCLK as the frequency reference to
generate the serial link data rate. The external clock
source must be crystal controlled and continuous. All
of the internal logic of PDX runs on internal clocks
that are derived from the external reference source or
extracted from the received data. The PDX’s clock
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P R E L I M I N A R Y
SUPERNET 3
multiplier is referenced to the rising edges of
LSCLK only.
In order to generate the serial output waveforms
conforming to the FDDI specifications, the external
reference clock must meet FDDI frequency and stability
requirements. Under normal conditions, the frequency
of LSCLK must be within the FDDI specified 50 ppm of
the received data for the PDX to operate optimally.
( Note: The 50 ppm is the tolerance of the crystal-
controlled source. )
The TX+/TX– serial outputs comply to the FDDI
SMF-PMD jitter allocation and typically contains less
than 0.4 ns peak-to-peak jitter at 125 MBaud.
The PDX accepts encoded PECL NRZI signal levels at
the RX+/RX– inputs and converts them to NRZ format.
The receiver circuit recovers data from the input stream
by regenerating clocking information embedded in the
serial stream. The PDX then clocks the unframed
symbol (5 bits) to the RDAT 4–0 interface on the falling
edge of RSCLK to the PLC-S core.
The PDX receiver uses advanced circuit techniques to
extract embedded clock information from the serial input
stream and recovers the data. Its operating frequency is
established by the reference at LSCLK. The PDX is
capable of tracking data correctly within 1000 ppm of
LSCLK (exceeds the frequency range defined by
the FDDI specification). FDDI 4B5B encoding scheme
ensures run-length limitation and adequate transition
density of the encoded data stream, while TP-PMD
achieves this on a statistical basis through data
scrambling. The PDX clock recovery circuit is
designed to meet and exceed a worst-case run-length
tolerance of 60-bits in order to function correctly with
both fiber-optic and twisted-pair PMDs. The actual
run-length tolerance is more than 1000 bits due to the
unique data recovery technique.
The PDX receiver has input jitter tolerance characteris-
tics that meet or exceed the recommendations of
Physical Layer Medium Dependent (PMD) FDDI docu-
ment. Typically, at 125 MBaud (8 ns/bit), the peak-to-
peak Duty-Cycle Distortion (DCD) tolerance is 1.4 ns,
the peak-to-peak Data Dependent Jitter (DDJ) toler-
ance is 2.2 ns, and the peak-to-peak Random Jitter (RJ)
tolerance is 2.27 ns. The total combined peak-to-peak
jitter tolerance is typically 5 ns with bit error rate (BER)
better than 2.5 X 10
-10
.