AM79C850KCW AMD [Advanced Micro Devices], AM79C850KCW Datasheet - Page 19

• Manufacturer Part Number: AM79C850KCW
• Description: SUPERNET-R 3
• Manufacturer: AMD [Advanced Micro Devices]

TRST
Test Reset (asynchronous TTL input, active low)
This input is provided for asynchronous initialization of
the TAP controller. When a logic 0 is applied, the TAP
controller must go to the Test-Logic-Reset state. If for
some reason TRST is not driven externally, the test logic
should behave as if a logic 1 were applied (internal
pull-up). This pin can not be used to initialize any
system logic.
Power and Ground (37 Pins)
GND
Ground (input)
There are 23 ground (GND) pins on the SUPERNET 3
chip. They must all be connected to a common external
ground reference.
V
+5 V Power (input)
There are 15 pins carrying +5-V power (VCC) on the
SUPERNET 3 chip. They must all be connected to a 5 V
SUPERNET 2 Features not
Supported
The
SUPERNET 3 in any mode.
Miscellaneous Changes from
SUPERNET 2
5% source.
CC
SUPERNET 3 supports the Tag Mode of operation
for the system-to-buffer-memory and network
(MAC)-to-buffer-memory interfaces. Non-Tag
mode of operation is no longer supported.
SUPERNET 3 supports three transmit queues:
Synchronous, Async0 and Async1. Async2 is no
longer supported.
The ‘Disable Carry’ (DISCRY) function is no
longer supported. Setting of the DISCRY bit in
the mode register 1 (MDREG1: bit 6) allowed
segmenting of the TRT, THT, TVX, and TMSYNC
registers into 4 and 5 bits each for diagnostic
purposes. This is no longer necessary due to the
testability enhancements.
Single-Frame Receive mode is no longer
supported.
Symbol Control is no longer supported in the MAC.
This function was used for diagnostics purposes to
transmit user-controlled data, control and violation
symbols to the PHY.
The HOLD function and associated logic is
eliminated and it is no longer supported.
The ‘Current Queue Almost Full’ (AFULL)
encoding of the QCTRL signals is modified to be
asserted for every clock after the AFULL boundary
following
features
are
not
supported
P R E L I M I N A R Y
SUPERNET 3
in
EXPLANATION OF ENHANCEMENTS
Status Pins
XS 3:0
Transmit Status pins (outputs)
An additional transmit status pin has been added to
provide more transmit information. The encoding of the
status pins is fully backward compatible with the
SUPERNET 2 chipset. The enhanced encoding is
enabled by setting the MENXS bit in the mode register 3
(MDREG3). The encoding of the XS pins is as follows:
XS3
is crossed until the queue is full while a Host write
request is asserted. Currently, the signal is
asserted for one clock only.
‘XDA_XACT’ and ‘XSA_XACT’ input signals are
provided for the external CAM (if implemented).
For increased robustness, all internal tri-state
busses will have a driven default state and will not
be allowed to float.
The Node Processor access interface has been
streamlined to two modes:
1) The FORMAC Plus asynchronous access
2) The PLC two-cycle synchronous access
There are four interrupt pins: two generated by the
two MAC status registers, one generated by the
AF and one generated by the PHY status register.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
mechanism for accessing all blocks.
mechanism for accessing all blocks.
XS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
XS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
XS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Indicated Status
Quiescent
Transmit Aborted
Token Issued
Reserved
Transmitting Syn-
chronous Queue
Transmitting Asyn-
chronous Queue 0
Transmitting Asyn-
chronous Queue 1
Reserved
Reserved
Initiated Claim
Initiated Beacon
Initiated Void
MAC Frame
Aborted
Void Frame
Aborted
Reserved
Reserved
AMD
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